Software Engineer I - VIP

Cadence Design Systems Inc. is seeking a motivated Software Engineer I – VIP in Belo Horizonte, Brazil. This role involves developing and maintaining software libraries for Cadence’s Verification IPs using C and C++, interfacing with HDL Languages like Verilog/SystemVerilog. The position offers an opportunity to solve challenging problems with state-of-the-art technology, focusing on software programming, debugging, and understanding SoC hardware architecture.

Must Have

• Proficient in software programming and good coding practices
• Good problem solving and debugging skills
• Understand software programming architecture, SoC hardware architecture and interfaces
• Complete Bachelors degree in Computer Science, Electrical Engineering or related fields
• Experience in Software Development
• Expertise in C/C++

Good to Have

• Knowledge of Verilog/SystemVerilog
• Knowledge of OVM/UVM verification methodologies
• Knowledge of the EDA tool flow, RTL Simulation

Perks & Benefits

• Competitive benefits

In this role, you will develop and maintain software libraries for Cadence’s Verification IPs, written in C and C++, interfacing with HDL Languages such as Verilog/SystemVerilog. This is a good opportunity to solve challenging problems in this area, using state of the art technology. If you want to know more about Cadence VIP, check Cadence Design Systems channel on YouTube.

Job Description:

• The candidate is expected to be proficient in software programming and follow good coding practices.
• They must have good problem solving and debugging skills.
• They should understand software programming architecture, SoC hardware architecture and interfaces.

Requirements:

• Complete Bachelors degree in Computer Science, Electrical Engineering or related fields
• Experience in Software Development
• Expertise in C/C++
• Scripting: Python, Perl, Bash
• Good verbal and written communication skills in Portuguese and English

Nice to have:

• Knowledge of Verilog/SystemVerilog
• Knowledge of OVM/UVM verification methodologies
• Knowledge of the EDA tool flow, RTL Simulation

Additional Job Details:

• Employment category: CLT
• Employment term: 40 hours/week.
• Competitive benefits.
• Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.