STA/EMIR IC Solutions Architect

1 Year ago • 10-12 Years

Devops

Job Description

Cadence is seeking leaders and innovators to make an impact on the world of technology. This role involves leading and executing technical campaigns, performing timing and correlation benchmarks with Cadence Tempus-Signoff tools, and delivering on timing analysis, ECO flows, Extraction, Power, EMIR, and physical design. Responsibilities include performing static timing analysis, glitch, noise analysis, extraction using Cadence Signoff tools, working with SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, and distributed/concurrent/hierarchical STA flows. The individual will collaborate with R&D and customers to enable timing analysis and ECO flows, perform timing correlation, tool feature benchmarking, and constraints validation. A good understanding of Place and Route, Clock Tree, RC Extraction, power, and UPF/CPF concepts is required, along with automation skills using scripting languages like Perl, Tcl, and Python. The role also includes delivering technical trainings and seminars.

Good To Have:

Basic understanding of Place and Route
Basic understanding of Clock Tree
Basic understanding of RC Extraction
Basic understanding of Power
Basic understanding of UPF/CPF concepts
Automation of flows using scripting languages (Perl, Tcl, python)

Must Have:

Expert in Static Timing Analysis
Knowledge of Physical Design
Knowledge of ECO flows
Knowledge of Power analysis
Knowledge of Extraction
Good understanding of Cadence Tools & flows like Tempus, Innovus or equivalent

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Individual will be leading and executing technical campaigns at various internal and external customers. Perform several timing & correlation benchmarks with Cadence Tempus -Signoff tool. Execute and deliver on timing analysis, ECO flows, Extraction, Power, EMIR and/or physical design and ensure integrity of delivered solutions. Individual should be able to efficiently work with Cadence R&D to enable various tool feature and close tool bug fixes. Work on various aspects of physical design including timing analysis, place and route, extraction, spice etc.

Job Responsibilities:

Perform Static timing analysis, glitch, noise analysis, extraction using Cadence Signoff tools. Executing and delivering on various aspects of Timing analysis flows, ECO flows, Power/EMIR, CAD tools and methodologies.
Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed, Concurrent and Hierarchical STA flows.
Work efficiently with R&D and customer to enable various timing analysis & ECO flows.
Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs.
Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction, power and UPF/CPF concepts.
Execute and lead Tempus timing signoff campaigns at existing and new customers.
Automation of flows using scripting languages (Perl, Tcl, python).
Deliver technical trainings and seminars within Cadence and customer sites.

Requirement :

12 years experience with Bachelors in Engineering or 10 years experience + Master in related field of VLSI, Semiconductor, Electrical or Computer Engineering.
Expert in Static Timing Analysis with knowledge of Physical Design and ECO flows, Power, Extraction.
Good understanding of Cadence Tools & flows like Tempus, Innovus or equivalent.
Have basic understanding of Place and route, power analysis.

Related tools/Keywords; Tempus, PT, STA, Quantus