Principal Design Engineer (Analog Mixed Signal / Memory)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview:

Lead Analog and Mixed Signal design of high speed memory interface analog components used in state-of-the-art DDR memory interface PHYs in leading edge technology nodes. Consisting of blocks such as IOs, amplifiers, comparators, drivers, duty cycle correctors, PLLs, DLLs, level shifters, etc. in advanced IC nodes in volume production.

As Principal Design Engineer, you will provide technical direction and coordination to the analog IC design team and Identify opportunities to advance technology of analog design and participate in strategic internal analog IP development.

Job Responsibilities:

• Design of High-Speed memory interface products at data rates up to and exceeding 36 Gbps on leading edge technology nodes (e.g. 5nm FinFET CMOS)
• Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
• Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections
• Work with Technical Team Leads in the areas of circuit design and architects
• Mentor Junior Design Engineers when the project need arises
• Work with global teams (US, India, China, EU), which work in different time-zones

Job Qualifications:

• Successful candidate should be BEng, MEng qualified or have an equivalent qualification.
• Minimum of 4 years of CMOS design experience, preferably in the area of CMOS SERDES, DDR or high-speed I/O IC design
• Should have a good understanding of jitter and signal equalization techniques
• Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
• Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification
• Cadence tool experience and design experience in <40nm technologies preferred.
• Lab test experience as part of silicon evaluation is advantageous

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

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About Us

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.