Job Description
Broadcom is seeking a Staff Physical Design Engineer to contribute to ASIC development for Storage/AI products. The role involves driving front-end and back-end implementation from RTL to GDSII, including synthesis, formal verification, floorplanning, timing and power convergence, and ECO implementation. The ideal candidate will have extensive experience in Place & Route, STA, and a strong understanding of physical design verification methodologies, with a focus on high-speed design and low-power techniques.
Good To Have:
- Proactive, collaborative, and creative approach to innovation, technical development, and consensus facilitation to influence optimal project results.
- Excellent time and task management, and interpersonal skills.
- Drive to automate flows.
Must Have:
- Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design.
- Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools.
- Proficiency in STA using Primetime and/or Tempus.
- Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation.
- Ability to drive front-end and back-end implementation from RTL to GDSII.
- Experience driving physical design and timing convergence of ASICs at both block and full-chip levels.
- Proficient in constraint generation and validation.
- Formal verification experience (Formality/Conformal).
- Strong problem-solving and ASIC development/debugging skills.
- Experience with low-power implementation techniques.
- Solid understanding of physical design verification methodology for debugging LVS/DRC issues.
- Good Understanding of Synopsys / Cadence tools.
- Familiarity with Calibre, IC Validator, and Redhawk (power analysis) tools.
- Scripting experience with Perl, Python, Tcl, and shell.
Job Description:
Broadcom is looking for a staff level physical design engineer. In this highly visible role, you will be contributing to ASIC for Storage/ AI products.
Qualifications:
- Education and Experience: Master's degree in Electronics/Computer Engineering with over 10 years of experience in physical design.
- Physical Design Expertise: Extensive experience in Place & Route using Synopsys FC or Cadence Innovus tools is essential. Proficiency in STA using Primetime and/or Tempus. Demonstrated knowledge of Clock Tree Implementation Techniques for High-Speed Design Implementation.
- Ability to drive front-end and back-end implementation from RTL to GDSII, including synthesis, formal verification, floorplanning, timing constraints, timing and power convergence, and ECO implementation.
- Experience driving physical design and timing convergence of ASICs at both block and full-chip levels.
- Proficient in constraint generation and validation.
- Formal verification experience (Formality/Conformal).
- Strong problem-solving and ASIC development/debugging skills.
- Experience with low-power implementation techniques.
- Solid understanding of physical design verification methodology for debugging LVS/DRC issues at the chip and block level.
Tools and Scripting:
- Good Understanding of Synopsys / Cadence tools.
- Familiarity with Calibre, IC Validator, and Redhawk (power analysis) tools.
- Scripting experience with Perl, Python, Tcl, and shell, with a drive to automate flows.
Highly Desired Qualities:
- Proactive, collaborative, and creative approach to innovation, technical development, and consensus facilitation to influence optimal project results.
- Excellent time and task management, and interpersonal skills.
Set alerts for more jobs like Staff Physical Design Engineer
Set alerts for new jobs by broadcom
Set alerts for new Design jobs in India
Set alerts for new jobs in India
Set alerts for Design (Remote) jobs
.png%3F1716476261&w=96&q=75){kind=small}
