ASIC Digital Design Engineer (Lead / Staff)
Job Description
- post-Si debug
- Micro-architecture and RTL design for Cores / subsystems.
- Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.
- Enable SW teams to use HW blocks.
- Qualify designs using static tool checks including Lint, CDC, LEC and CLP.
- Synthesis, LEC and Netlist CLP.
- Report status and communicate progress against expectations.
- Health: Qualcomm offers a world-class health benefit option providing world-class coverage to employees and their eligible dependents.
- Wealth: Our programs are designed to help employees build and prepare for a financially secure future.
- Self: Our self and family resources help you build emotional/mental strength and resilience, as well as define your purpose — in life and at work.
- Wellbeing: Qualcomm’s wellbeing programs and resources offer support to help employees Live+Well and Work+Well, so they can unlock their full potential at home, at work, and everywhere between.
Job Description
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide.
Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.
Key Responsibilities
- Micro-architecture and RTL design for Cores / subsystems.
- Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence.
- Enable SW teams to use HW blocks.
- Qualify designs using static tool checks including Lint, CDC, LEC and CLP.
- Synthesis, LEC and Netlist CLP
- Report status and communicate progress against expectations.
Preferred Qualifications
- 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs
- Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains
- Familiar with UPF and power domain crossing
- Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP
- Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
- Experience in low power design methodology and clock domain crossing designs
- Experience in Spyglass Lint/CDC checks and waiver creation
- Experience in formal verification with Cadence LEC
- Understanding of full RTL to GDS flow to interact with DFT and PD teams
- Expertise in Perl/TCL/Python language
- Experienced in database management flows with Clearcase/Clearquest.
- Expertise in post-Si debug is a plus
- Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members.
- Team player, self-motivated, should be able to work with minimal supervision.
