Lead Verification Engineer
12 Months ago • 4 Years +
Research Development
Job Description
Lead Verification Engineer at Cadence requires 4+ years of Design Verification experience with SV/UVM. Strong background in functional verification fundamentals, environment planning, test plan generation, and environment development is essential. Experience leading projects from concept to verification closure and hands-on UVM and System Verilog coding experience are required.
Good To Have:
- Memory IP Verification
- DDR/HBM/GDDR
- Project Leadership
- Verification Closure
Must Have:
- Design Verification
- SV/UVM Experience
- Functional Verification
- Environment Development
Perks:
- Impact on Technology
- Leader Development
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- 4+ years of Design Verification experience with SV/UVM
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
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