Job Description
Cadence is seeking a Lead Design Engineer for an IP development team, focusing on Design Verification. The role involves developing robust UVM testbenches, performing functional and potentially formal verification, and participating in emulation qualification for Serial and Interface Design IPs like PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C. The ideal candidate will have 5-7 years of experience, strong problem-solving, analytical, and communication skills, and a passion for quality work.
Must Have:
- Design Verification for IP development
- UVM testbench development
- UVM functional verification
- Understanding design and producing detailed verification strategy and test plan
- Strong problem solving, analytical and debug skills
- Excellent verbal and written communications skills
- Experience with Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
BE/BTECH/ME/MTECH Or Equivalent Degree
EXP:5-7yrs
Design Verification role for IP development team.
- Position is based in Bangalore/Noida, part of Cadence IP Group.
Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
- UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
- In addition to UVM functional verification, role could involve Formal verification of complex design modules.
- In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
- Understand design and produce detailed verification strategy and test plan.
Self-starter and learner with passion for getting the job done on time with great quality.
- Strong problem solving, analytical and debug skills
- Excellent verbal and written communications skills
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