Principal Product Engineer(Serdes IP)

Join Cadence's innovative IP team to develop best-in-class digital and mixed-signal IP solutions, focusing on high-performance IP across protocols like PCIe. This role is crucial for supporting post-silicon bring-up for customers, involving detailed analysis, root-cause investigations, and collaboration with FW teams. You will leverage AI-powered tools to enhance productivity and deliver high-quality customer solutions, working with global teams and traveling as needed.

Must Have

• Lead bring‑up and debug of CDNS SerDes PHY IPs for customer silicon.
• Perform detailed analysis of signal integrity, jitter, and BER performance.
• Drive root‑cause investigations for silicon issues and propose corrective actions.
• Use oscilloscopes, BERTs, protocol analyzers, and other lab equipment to measure CDNS PHY function and performance.
• Maintain CDNS Testchip bench locally to duplicate and debug customer issues.
• Collaborate with FW teams to validate SerDes initialization sequences and support FW debugging.
• Work with global (US, west and east coast) teams in different time-zones.
• Travel as needed to support post‑silicon bring‑up and customer engagements.
• Leverage AI-powered tools and assistants to enhance productivity and improve decision making.
• Apply AI-powered analytics tools to extract insights from complex datasets.
• Bachelor’s in computer science or electrical engineering + 7 years of related experience, or Masters +5 years of related experience.
• Very strong experience in silicon bring-up with lab equipment (Scope/Bert/PCIe exerciser/analyzer).
• Very strong experience in PCIe protocol, PCIe LTSSM link stable analysis, PCI Compliance test.
• Familiar with board design, ability to read schematics and conduct SI/PI analysis and review for customer board implementation.
• Strong communication and organizational skills.
• Ability to prioritize cases, anticipate escalations.

Good to Have

• Experience on Ethernet or USB or DP or JESD.
• Experience on Serdes components like Tx FFE, Rx CTLE& DFE& VGA&FFE.
• Experience on DSP based Serdes receiver.
• Experience on PLL algorithm.

About Us

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the world’s most innovative companies, delivering extraordinary electronic products—from chips to boards to systems—for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success.

Position Overview

We invite you to join a growing and innovative IP team dedicated to building best-in-class digital and mixed-signal IP solutions. You will work alongside seasoned professionals developing high-performance IP across protocols such as PCIe. In this role, you will be integral to the organization’s efforts to support post-silicon bring-up for customers.

Key Responsibilities

• Lead bring‑up and debug of CDNS SerDes PHY IPs for customer silicon.
• Perform detailed analysis of signal integrity, jitter, and BER performance.
• Drive root‑cause investigations for silicon issues and propose corrective actions.
• Use oscilloscopes, BERTs, protocol analyzers, and other lab equipment to measure CDNS PHY function and performance. Maintain CDNS Testchip bench locally to duplicate and debug the issues that external customers are dealing with.
• Collaborate with FW teams to validate SerDes initialization sequences, support FW debugging related to SerDes bring‑up.
• Working with global (US, west and east coast) teams in different time-zones.
• Travel as needed to support post‑silicon bring‑up and customer engagements.
• AI Incorporation: Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables. Apply AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets.

Skills & Qualifications

Required

• Bachelor’s in computer science or electrical engineering + 7 years of related experience, or Masters +5 years of related experience.
• Very strong experience in silicon bring-up with lab equipment (Scope/Bert/PCIe exerciser/analyzer).
• Very strong experience in PCIe protocol, PCIe LTSSM link stable analysis, PCI Compliance test.
• Familiar with board design. Ability to read schematics and conduct SI/PI analysis and review for customer board implementation.
• Strong communication and organizational skills.
• Ability to prioritize cases, anticipate escalations.

• Experience on Ethernet or USB or DP or JESD will be plus.
• Experience on Serdes components like Tx FFE, Rx CTLE& DFE& VGA&FFE will be plus.
• Experience on DSP based Serdes receiver will be plus.
• Experience on PLL algorithm will be plus.