Power Management Design Engineer

1 Day ago • 5-8 Years • $140,000 PA - $210,000 PA

Project Management

Job Description

This role involves designing and developing next-generation power control systems for ASICs using the latest technology nodes. The candidate will cover all aspects of the VLSI development cycle, including architecture, micro-architecture, and RTL design, collaborating closely with verification, synthesis, and physical design teams to ensure design convergence and successful implementation.

Good To Have:

Expertise in post-Si debug is a plus

Must Have:

5 to 8 years of strong experience in digital front end design for ASICs
Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
Familiar with UPF and power domain crossing
Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC
Understanding of full RTL to GDS flow to interact with DFT and PD teams
Expertise in Perl, TCL language
Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India
Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
Design and implement defined tasks independently.
Work in close coordination with Systems, Verification, SoC team, SW team, PD & DFT teams to get the goals completed.
Analyze reports/waivers or run various tools: Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Perks:

Health: Qualcomm offers a world-class health benefit option providing world-class coverage to employees and their eligible dependents.
Wealth: Our programs are designed to help employees build and prepare for a financially secure future.
Self: Our self and family resources help you build emotional/mental strength and resilience, as well as define your purpose — in life and at work.
Wellbeing: Qualcomm’s wellbeing programs and resources offer support to help employees Live+Well and Work+Well, so they can unlock their full potential at home, at work, and everywhere between.

Add these skills to join the top 1% applicants for this job

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Job Posting Date

2025-09-26

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Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Candidate will be responsible for design/developing next generation power control systems. Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD teams for design convergence.

Skills/Experience Sr Engineer / Staff Engineer

5 to 8 years of strong experience in digital front end design for ASICs
Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
Familiar with UPF and power domain crossing
Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC
Understanding of full RTL to GDS flow to interact with DFT and PD teams
Expertise in Perl, TCL language
Expertise in post-Si debug is a plus
Good documentation skills
Should possess good communication skills to ensure effective interaction with Engineering Management and team members.
Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision

Responsibilities

Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India
Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
Design and implement defined tasks independently.
Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.
Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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Pay range and Other Compensation & Benefits:

$140,000.00 - $210,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.