SOC Clock Implementation Engineer

12 Months ago • 5-7 Years

Software Development & Engineering

Job Description

Join a well-funded hardware startup focused on Risc-V based SOC computing platforms. As an SOC Clock Implementation Engineer, you will redefine silicon and contribute to industry transformation. You will collaborate with talented engineers to create designs that push performance, energy efficiency, and scalability boundaries. This role offers a creative and flexible work environment with a shared vision to build world-changing products. Key responsibilities include defining clock methodology to influence architectural changes, planning and implementing clocking solutions, developing simulation models, and overseeing physical implementation for the SOC. You will also develop and maintain clock tree synthesis flows, analyze clock tree quality, and conduct clock verification. This role requires engagement with various teams including RTL, Integration, LEC, STA, Power, EMIR, and LV.

Must Have:

Define clock methodology for early architectural changes
Plan and implement clocking solutions
Develop simulation models for clocking
Manage physical implementation of clocking
Develop clock tree synthesis flow
Analyze clock tree quality and verification
Engage with RTL, Integration, LEC, STA, Power, EMIR, LV teams
5-7 years experience with clock methodology for high performance SoCs
Experience with advanced process nodes (7/5/3nm)
Experience with clock arch planning and custom clocking
Experience with synthesis, place & route, STA, Spice
Strong knowledge of CMOS circuits and low power design
Working knowledge of EM, IR, Top-level integration
Working knowledge with Verilog/System Verilog
Strong scripting skills (TCL/Python)
Problem-solving, communication, organization skills
Self-starter, highly motivated
Ability to work cross-functionally
BS with 7 years or MS with 5 years of experience

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Join a cutting-edge and well-funded hardware startup as an SOC Clock Implementation Engineer. Our mission is to reimagine silicon and create Risc-V based SOC computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

Define clock methodology to influence early clock arch changes, plan and implement clocking solutions, develop simulation models, and physical implementation for the SOC.
Develop and maintain clock tree synthesis flow for block consumption.
Analyze clock tree quality and clock verification.
Engage with RTL, Integration, Block level, LEC, STA, Power, EMIR and LV teams.

Qualifications

5-7 years of experience with clock methodology development for high performance SoCs in advanced process nodes (7/5/3nm).
Experience with clock arch planning, clock tree synthesis flow, implementing custom clocking solutions, quality metrics and clock verification.
Experience with synthesis, place & route, STA and Spice.
Strong knowledge of CMOS circuit, low power design.
Working knowledge of EM, IR, Top-level integration.
Working knowledge with verilog/system verilog.
Strong scripting skills preferably in TCL/Python.
Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
Self starter and highly motivated
Ability to work cross-functionally with various teams and be productive under aggressive schedules