Application Engineer I: Digital Verification & Simulation - VIP

Cadence

| Belo Horizonte, State of Minas Gerais, Brazil (On Site) | Full Time | 1 day ago

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Job Summary

Cadence Design Systems Inc. is seeking an Application Engineer I for Digital Verification & Simulation - VIP in Belo Horizonte, Brazil. This role involves becoming an expert in Digital Verification & Simulation methodologies, providing technical support to customers, deploying industry-leading technology, and developing innovative solutions. The engineer will focus on RTL-level verification products, particularly Cadence Verification IP Solutions, and collaborate with customers to ensure their success.

Must Have

Provide technical support for RTL verification solutions, focusing on Cadence Verification IP.
Conduct root cause analysis and resolve customer technical issues.
Develop and run cases to verify problems, create workarounds, test, and deliver R&D fixes.
Collaborate with R&D on issues.
Author application notes and provide documentation feedback.
Use scripting languages like TCL and Python for flow development and automation.
Engage in pre-sales and post-sales technical campaigns.
Complete bachelor’s in Electrical, Computer, Electronics, Control and Automation, Systems Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas.
Excellent verbal and written communications skills in Portuguese and English.

Good to Have

Exposure to RTL (Verilog or VHDL).
Knowledge of verification methodologies such as UVM.
Knowledge of industry standard protocols such as AMBA, USB, Ethernet.
Knowledge of memory models.
Experience in scripting languages such as TCL and Python.
Exposure to microelectronics, semiconductors, or EDA, with experience in functional verification (simulation), model verification, or Verification IP.
Knowledge of Cadence verification tools.

Perks & Benefits

Competitive benefits

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Application Engineer I: Digital Verification & Simulation - VIP to work with us.

As an Application Engineer, you will be trained to become an expert in Digital Verification & Simulation methodologies in the System Verification Group - Technical Field Operations (TFO-SVG). The TFO-SVG group works with Xcelium, Palladium, Protium, Jasper, VIPs, Perspec, and other Cadence Digital Functional Verification tools.

The application engineers provide technical support, enabling customers to effectively deploy our industry-leading technology, focused on RTL-level verification products. You will be in a Digital Verification & Simulation focused team working with our Verification IP Solutions, complimentary tools, and its customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success, coming up with innovative solutions to address the industry’s most challenging problems.

Job Description:

Activities focused on the Functional Verification field as mentioned above, reporting to higher management.
Provide technical support in engagements with customers and field personnel in RTL verification solutions focused on the Cadence Verification IP solutions and other supporting technologies.
Contribute to technical and sales meetings interacting with engineers, technical leads and executives.
Conduct root cause analysis and provide resolution to customer technical issues.
Develop and run cases to verify problems, create workarounds, test and deliver R&D fixes.
Close collaboration with R&D on issues using established protocols.
Author application notes and help provide feedback on documentation.
Use scripting languages like TCL and Python for flow development, automation and enhancing design methodologies.
Engage with AE team on pre-sales and post-sales technical campaigns from the technical side, working along with Sales and Marketing to plan deployment, conduct technical evaluations and support.

Requirements:

Complete bachelor’s in Electrical Engineering, Computer Engineering, Electronics Engineering, Control and Automation Engineering, Systems Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas.
Excellent verbal and written communications skills in Portuguese and English.
Good problem-solving skills.
Strong inter-personal and communication skills.
A strong interest in debug and contributing to customer success with related technical interest in EDA, hardware development (HDL's), Logic Design/Verification and the semiconductor industry.

Nice to have:

Exposure to RTL (Verilog or VHDL).
Knowledge of verification methodologies such as UVM is a plus.
Knowledge of industry standard protocols such as AMBA, USB, Ethernet etc. is a plus.
Knowledge of memory models is a plus.
Experience in scripting languages such as TCL and Python is a plus.
Exposure to microelectronics, semiconductors and or EDA, with experience on functional verification (simulation), model verification, or Verification IP.
Knowledge of Cadence verification tools is a plus.

Additional Job Details:

Employment category: CLT.
Employment term: 40 hours/week.
Competitive benefits.
Av. do Contorno 5800, Savassi, Belo Horizonte, Minas Gerais, Brazil

About Cadence Design Systems:

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.

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