Application Engineer I: Digital Simulation/Verification & Agentic AI

Cadence Design Systems Inc. is seeking an Application Engineer I for Digital Simulation/Verification & Agentic AI in Belo Horizonte, Brazil. This role involves supporting customers with Cadence's digital verification and simulation tools, specifically Xcelium and Verisium. The engineer will learn and apply Agentic AI to automate verification tasks, improve coverage, and assist in adopting AI-driven solutions, working in a dynamic, fast-paced global environment.

Must Have

• Provide technical support for Cadence verification products
• Assist with Simulation Flows using Xcelium
• Use AI tools to simplify repetitive tasks and improve verification speed
• Write simple scripts (Python or TCL) for systems automation
• Work with UVM-based environments and learn coverage analysis
• Collaborate in technical discussions and training
• Complete Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field
• Knowledge of SystemVerilog and digital design concepts
• Familiarity with scripting languages (Python, TCL)
• Understanding of RTL design and coding (Verilog, VHDL)
• Excellent written and verbal communication skills in English and Portuguese
• Strong analytical and problem-solving skills

Good to Have

• Experience with Unix and C/C++
• Knowledge of design fundamentals such as architecture, micro-architecture, HDL synthesis, and timing
• Verification skills including UVM testbench architecture, development and debugging, System Verilog, and SVA
• Understanding of SoC architecture fundamentals
• Familiarity with embedded software development and HW/SW co-design and co-verification
• Proficiency in scripting languages (Perl, Python, TCL, Bash, etc.)

Perks & Benefits

• Competitive benefits

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

As an Application Engineer, you will support customers and internal teams in digital verification and simulation flows using Cadence Simulation and Verification tools. You will be part of System & Verification Group (TFO-SVG) in the Systems Verification Simulation group. This role focuses on learning and applying Agentic AI to make verification tasks smarter and more efficient. You will work closely with senior engineers to automate processes, improve coverage, and help customers adopt innovative AI-driven solutions.

Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world, at this opportunity you will work with cutting-edge Agentic AI in real-world simulation/verification flows and hands-on experience with industry-leading tools like Cadence Xcelium™, Verisium.

Job Description:

• As an Application Engineer you will be responsible to provide technical support, helping Cadence customers to effectively deploy our industry leading Verification products and Assist with Simulation Flows, helping set up and run simulations using Xcelium.
• Learn and Apply Agentic AI: Use AI tools to simplify repetitive tasks and improve verification speed.
• Systems Automation: Write simple scripts (Python or TCL) to automate routine steps.
• Support Verification Tasks: Work with UVM-based environments and learn coverage analysis.
• Collaborate with Teams: Join technical discussions and training sessions to grow your skills.

Requirements:

• Complete Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field.
• Knowledge of SystemVerilog and digital design concepts.
• Interest in AI technologies and their application in engineering workflows.
• Familiarity with scripting languages (Python, TCL).
• Good communication skills and willingness to learn.
• Understanding of RTL design and coding (Verilog, VHDL)
• Excellent written and verbal communication skills in English and Portuguese.
• Strong analytical and problem-solving skills.

Nice to have:

• Experience with Unix and C/C++
• Knowledge of design fundamentals such as architecture, micro-architecture, HDL synthesis, and timing
• Verification skills including UVM testbench architecture, development and debugging, System Verilog, and SVA
• Understanding of SoC architecture fundamentals
• Familiarity with embedded software development and HW/SW co-design and co-verification
• Proficiency in scripting languages (Perl, Python, TCL, Bash, etc.)

Additional Job Details:

• Employment category: CLT
• Employment term: 40 hours/week.
• Competitive benefits.
• Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.

We’re doing work that matters. Help us solve what others can’t.

About Us

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.