ASIC Design Engineer - Cisco Silicon One

Join the Cisco Silicon One Front-End Design team, at the core of silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation. You will write and review micro-architecture specifications, implement RTL, contribute to full chip integration, collaborate with verification and physical design teams, and support design methodology. You will also perform debug, root-cause analysis, and post-silicon validation in the lab.

Must Have

• B.Sc./M.Sc. in Electrical Engineering from a top university
• 3+ years of experience in a relevant field
• RTL design experience
• Familiarity with UVM and functional verification methodologies

Good to Have

• Experience with MATLAB simulations and bit-exact modeling environments
• Familiarity with mixed-signal systems and environments
• Knowledge and hands-on experience with Clock Domain Crossing (CDC)

Perks & Benefits

• Work with impact, powering the future for customers and the world
• Limitless opportunities for learning and growth with technology, resources, and industry experts
• Benefits designed to support well-being, time away, and family

Job Description

Meet the Team

Join the Cisco Silicon One Front-End Design team, at the core of silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.

We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible.

Silicon One™ is transforming the industry with a unified, programmable architecture powering future routing portfolio and shaping the Internet for decades to come.

Your Impact

• Write and review micro-architecture specifications
• Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
• Contribute to full chip integration, timing methodology, and analysis
• Collaborate with verification engineers to resolve bugs and achieve coverage closure
• Work with the physical design team to close timing and PnR issues
• Support design methodology evolution and best practices
• Perform debug, root-cause analysis, and post-silicon validation in the lab

Minimum Qualifications

• B.Sc./M.Sc. in Electrical Engineering from a top university
• 3+ years of experience in a relevant field
• RTL design experience
• Familiarity with UVM and functional verification methodologies

Preferred Qualifications

• Experience with MATLAB simulations and bit-exact modeling environments
• Familiarity with mixed-signal systems and environments
• Knowledge and hands-on experience with Clock Domain Crossing (CDC)

Why Cisco?

At , we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are , and our power starts with you.