CAD Engineer - Timing for Gate-Level Flows & Methodologies

As a member of our STA CAD team, you will:
 • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems