CAD Engineer - Timing for Gate-Level Flows & Methodologies
3 Months ago • All levels • $181,100 PA - $318,400 PA
Level Design
Job Description
As a member of the Silicon Technologies group, you will design and manufacture high-performance, power-efficient processors and systems-on-chip (SoCs). You will ensure Apple products and services handle tasks efficiently. In this role, you will be responsible for crafting and building the technology that powers Apple's devices, enabling users to do what they love with their devices. You will be an integral part of improving the performance of Apple Silicon by being responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first-time right silicon.
Good To Have:
- Work with EDA vendors
- Incorporate new capabilities
Must Have:
- Develop and maintain gate-level STA flows
- Debug timing closure issues
- Improve STA methodology efficiency
- Develop timing analysis scripts
- Support timing constraint verification
- Analyze timing paths
- Debug post-silicon timing
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon.
As a member of our STA CAD team, you will:
• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems
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