CPU STA Engineer, Senior Lead
Job Description
- Extensive experience in Place & Route with FC or Innovus.
- Complete ASIC flow with low power, performance and area optimization techniques.
- Experience with STA using Primetime and/or Tempus.
- Proficient in constraint generation and validation.
- Experience of multiple power domain implementation with complex UPF/CPF definition.
- Formal verification experience (Formality/Conformal).
- Perl/Tcl, Python, C++ skills are needed.
- Strong problem solving and ASIC development/debugging skills.
- Experience with CPU micro-architecture and their critical path.
- Low power implementation techniques experience.
- High speed CPU implementation.
- Clock Tree Implementation Techniques for High Speed Design Implementation.
- Exposure to Constraint management tool and Verilog coding experience.
- Qualcomm offers a world-class health benefit option providing world-class coverage to employees and their eligible dependents.
- Our programs are designed to help employees build and prepare for a financially secure future.
- Our self and family resources help you build emotional/mental strength and resilience, as well as define your purpose — in life and at work.
- Qualcomm’s wellbeing programs and resources offer support to help employees Live+Well and Work+Well, so they can unlock their full potential at home, at work, and everywhere between.
Job Posting Date
2025-10-23
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
• Extensive experience in Place & Route with FC or Innovus is an absolute must
• Complete ASIC flow with low power, performance and area optimization techniques
• Experience with STA using Primetime and/or Tempus is required
• Proficient in constraint generation and validation
• Experience of multiple power domain implementation with complex UPF/CPF definition required
• Formal verification experience (Formality/Conformal)
• Perl/Tcl, Python, C++ skills are needed
• Strong problem solving and ASIC development/debugging skills
• Experience with CPU micro-architecture and their critical path
• Low power implementation techniques experience
• High speed CPU implementation
• Clock Tree Implementation Techniques for High Speed Design Implementation are required
• Exposure to Constraint management tool and Verilog coding experience
Master's degree in Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
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