Design Verification Engineer Graduate (Video Silicon IP) - 2026 Start (BS/MS)

Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions. As a Design Verification Engineer Graduate, you will play a crucial role in delivering a Video Codec IP by generating test benches, running simulations, developing test plans, leading bug tracking, automating regression testing, and closing coverage. This role involves interfacing with architects and ASIC/FPGA design engineers. We are looking for talented individuals to join our fast-growing team in 2026, offering opportunities to pursue bold ideas and tackle complex challenges.

Must Have

• Currently pursuing a Master's in computer science/electrical engineering or a related technical discipline
• Knowledge of modern verification methodologies, such as UVM/OVM
• Good programming skills with SystemVerilog to work on constrained randomization and functional coverage model
• Familiar with RTL design (SystemVerilog) and SVA (SystemVerilog Assertion)
• Ability to commit to an onboarding date by end of year 2026

Good to Have

• Familiar with at least one scripting language, such as Python/Perl
• Familiar with SystemC, or DPI

Perks & Benefits

• Day one access to medical, dental, and vision insurance
• 401(k) savings plan with company match
• Paid parental leave
• Short-term and long-term disability coverage
• Life insurance
• Wellbeing benefits
• 10 paid holidays per year
• 10 paid sick days per year
• 17 days of Paid Personal Time (prorated upon hire with increasing accruals by tenure)
• Additional discretionary bonuses/incentives
• Restricted stock units

ResponsibilitiesOur team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. We are looking for talented individuals to join our team in 2026. As a graduate, you will get opportunities to pursue bold ideas, tackle complex challenges, and unlock limitless growth. Launch your career where inspiration is infinite at ByteDance Successful candidates must be able to commit to an onboarding date by end of year 2026. Please state your availability and graduation date clearly in your resume. Candidates can apply to a maximum of two positions and will be considered for jobs in the order you apply. The application limit is applicable to ByteDance and its affiliates' jobs globally. Applications will be reviewed on a rolling basis - we encourage you to apply early. Responsibilities - As a Design Verification engineer, you will be taking on an important role in helping deliver a Video Codec IP by generating test benches and running simulations. You will interface with architects and ASIC/FPGA design engineers to develop test plans, lead bug tracking, automate regression testing, and close coverage.

Qualifications

Minimum Qualifications

• Currently pursuing a Master's in computer science/electrical engineering or a related technical discipline
• Knowledge of modern verification methodologies, such as UVM/OVM.
• Good programming skills with SystemVerilog to work on constrained randomization and functional coverage model.
• Familiar with RTL design (SystemVerilog) and SVA (SystemVerilog Assertion)

Prefered Qualifications

• Familiar with at least one scripting language, such as Python/Perl.
• Familiar with SystemC, or DPI

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