FVCTO - Formal Verification Architect

Join Intel's Formal Verification Central Tech Office (FVCTO) as a Formal Verification Engineer. You will be responsible for verifying microarchitecture using industry-standard Formal Verification tools and technologies, applying model checking and equivalence checking algorithms on world-class design IPs and SOCs for Server, Client, and Graphics. This role involves defining formal verification scope, deploying advanced formal techniques, creating abstraction models, and ensuring high-quality design delivery on schedule. You will also analyze new methodologies, evaluate tools, and collaborate with design teams to resolve complex problems.

Must Have

• Verify microarchitecture using Formal Verification tools.
• Utilize hardware architecture and RTL implementation details.
• Define Formal Verification scope and strategy.
• Create abstraction models for design convergence.
• Develop comprehensive formal verification test plans.
• Apply abstraction techniques to converge complex designs.
• Deliver high-quality design on schedule.
• Bachelor's with 9 years, Master's with 6 years, or PhD with 4 years experience.
• Proficiency in RTL languages (System Verilog/VHDL).
• Proficiency in Assertion languages (SVA) and formal verification.

Good to Have

• Understanding of formal verification technology fundamentals.
• Experience with model checking and writing formal assertions.
• Knowledge of formal verification principles and methods.
• Familiarity with computer architecture, digital design, and verification.
• Experience in formal verification domain research.

Perks & Benefits

• Competitive pay
• Stock
• Bonuses
• Health benefits
• Retirement benefits
• Vacation

Job Description:

Do Something Wonderful!

put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world-changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at , we are building a better tomorrow.

Who We Are

The Data Center and AI (DCAI) delivers leadership Xeon products to cloud, datacenter and AI customers through development of industry leading IPs that enhances product performance and competitiveness in both Xeon and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building blocks for the Xeon server SOCs.

Who You Are

Come join the winning team at FVCTO (Formal Verification Central Tech Office). As a Formal Verification Engineer, you will be responsible the following but not limited to:

• Verify microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs and SOCs for Server, Client and Graphics.
• Use the hardware architecture design and RTL implementation details.
• Define the Formal Verification scope, deploy the right strategy to prove correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design.
• Carve out the right boundaries for the design, create comprehensive formal verification test plans, track, verify, apply abstraction techniques, and converge on complex designs to deliver a high-quality design on schedule and articulate the ROI.
• Analyses new methodologies, evaluates new tools, and corroborates results.
• Work with vendors to resolve hard design and tool problems.

In addition to the qualifications, a successful candidate will demonstrate:

• Problem solving and debugging skills.
• Willingness to work closely with various design teams and cross site teams.
• Verbal and written communication skills.
• Motivated, self- directed and can work effectively both independently and in a team environment.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must possess the following:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 9 years relevant experience or schoolwork OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 6 years relevant experience or schoolwork OR PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field with 4 years relevant experience or schoolwork

Experience in the following:

• RTL languages like System Verilog or VHDL Assertion languages like SVA, formal verification.

Preferred Qualifications

Experience with:

• The fundamentals of formal verification technology, including model checking and writing formal assertions to express architectural intent of designs
• Formal verification principles and methods
• Computer architecture, digital design and verification methods Research in formal verification domain