Interconnect Design/RTL

Network-on-Chip interconnects architecture aims to replace traditional interconnects, such as buses or crossbars, with one that is highly structured, and scalable with layered communication. This position is responsible for Micro-architecture specifications and detailed design of interconnects (NoCs/NICs) and related IPs based on system-level use-cases. The role involves defining new platform interconnect solutions across various NXP business lines, collaborating with SoC, verification, and physical design teams to optimize NoC topology, and developing innovative solutions for interconnect partitioning. The individual will also ensure performance requirements are met and work with third-party NoC technology providers.

Must Have

• Responsible for Micro-architecture specifications and detailed design of interconnects (NoCs/NICs) and related IPs.
• Define new platform interconnect solutions across IoT/Automotive/Edge Processing/Radar and other domains.
• Collaborate with SoC, verification, physical design, and core teams for optimal NoC topology/structure.
• Develop innovative solutions for partitioning the Interconnect.
• Responsible for (Full/IO) coherent interconnect and interconnect in various cores/subsystems.
• Ensure Interconnect meets all performance requirements.
• Work with third-party NoC technology providers.
• BTech/MTech/Ph.D. in Electrical/Computer Engineering with at least 5 years of relevant experience.
• Understand interconnect protocols like AHB/AXI/ACE/ACE-Lite/NoC concepts.
• Good knowledge of Digital Design and RTL development, including Verilog RTL coding.
• Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols, and virtualization.
• Working knowledge of Synthesis, DFT, verification, and silicon debug.
• Working knowledge of Lint, CDC, PLDRC, CLP.
• Basic Knowledge of System Architecture, system design, SOC micro-architecture.

Good to Have

• Experience in designing or architecting complex SoCs in leading-edge process nodes.
• Exposure to ISO26262-compliant and mixed-criticality architectures.
• Ability to work at the system level, identifying optimal partitioning of solutions between hardware and software.
• Track record of assessing performance, power, and area tradeoffs.
• Experience in defining IP components to solve system issues.
• High motivation and results orientation.
• Strong problem-solving skills.
• Excellent interpersonal skills, including written and verbal communication.
• Teamwork, negotiation, and presentation skills.
• Willing and able to mentor junior engineers.

Perks & Benefits

• Online and offline learning opportunities for career development.
• Commitment to sustainability.
• Inclusive work environment.
• Programs focused on diversity, inclusion and equality.

Business Line Description:

NXP's Advance Chip Engineering (ACE) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXP's Automotive, Edge, and Radar Processing business lines. MME's SoC Hardware Architecture team produces architectural solutions covering the very wide range of SoCs required by the business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low-power devices to highly integrated, high-performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.

Jobs Summary

Network-on-Chip interconnects architecture aims to replace traditional interconnects, such as buses or crossbars, with one that is highly structured, and scalable with layered communication. In Nxp this has been used extensively in various product categories. This position will be

• Responsible for Micro-architecture specifications and detailed design of interconnects (NoCs/NICs) and related IPs based on the understanding of system-level use-cases
• Work with multiple platform architecture domains, such as I/O’s, Audio, Networking, PCI-E, CPU/GPU/Multimedia/DDR, etc. to define new platform interconnect solutions across IoT/Automotive/Edge Processing/Radar and other domains
• Actively work very closely with SoC team, verification team, physical design team, Soc Floorplan, and core teams to come up with appropriate NoC topology/structure which is optimal in area/performance. Collaborate will the team throughout the entire product development cycle to ensure your solution is successfully deployed in commercial product
• Come up with innovative solutions for partitioning the Interconnect, which will be implementation friendly.
• Responsible for (Full/IO) coherent interconnect, interconnect in various cores/ subsystems solutions
• Actively work with the SoC performance team to make sure the Interconnect meets all the performance requirements, and with the silicon validation team to co-relate pre-silicon and post-silicon assumptions.
• Work very closely with the third-party NoC technology providers to decide on the direction of future interconnect technology in Nxp products

Key Challenges:

• Experience in designing or architecting complex SoCs in leading-edge process nodes with multiple independent compute environments
• Exposure to ISO26262-compliant and mixed-criticality architectures
• Ability to work at the system level, identifying optimal partitioning of solutions between hardware and software, working closely with software architects
• Track record of assessing performance, power, and area tradeoffs and determining the correct balance for a given product type
• Experience in defining IP components to solve system issues.
• High motivation and results orientation
• Strong problem-solving skills
• Excellent interpersonal skills, including written and verbal communication
• Teamwork, negotiation, and presentation skills
• Willing and able to mentor junior engineers

Job Qualifications:

• BTech/MTech/Ph.D. in Electrical/Computer Engineering or other similar disciplines with at least 5years of relevant experience.
• Understand interconnect protocols like AHB/AXI/ACE/ACE-Lite/NoC concepts.
• Good knowledge of Digital Design and RTL development - Hands-on experience with SoC Design, Verilog RTL coding
• Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols, and virtualization
• Working knowledge of Synthesis, DFT, verification, and silicon debug.
• Working knowledge of Lint, CDC, PLDRC, CLP, etc
• Basic Knowledge of System Architecture
• Familiarly with system design, SOC micro-architecture, and/or design

Job locations:

• Noida, India
• Bengaluru, India

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NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com

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Bright Minds. Bright Futures.

We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

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We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality

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