Layout Engineer

The Layout Engineer will be part of the Central Engineering Group's Library Group, focusing on circuit design for memory, I/O, and Standard Cells. Responsibilities include applying layout guidelines, scheduling timelines, floor-planning, and completing quality layout and verification within planned schedules. The role requires strong layout knowledge, experience with Cadence and CALIBRE/Hercules tools, and expertise in submicron processes and digital layout. The engineer will also contribute to new methodologies and team collaboration.

Must Have

• Understand and apply all necessary layout guidelines (standard cells, I/O memories)
• Apply new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule
• Get up to speed quickly for new methodologies
• Open to new ideas and communicate well with others in the library team
• Strong experience in memory layout design and physical verifications
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL)
• Experienced in CALIBRE verification tools
• Good experience in Floor-planning, hierarchy layout and chip integration
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines
• Self-reliant, with ability to work independently as well as a team
• Good leadership quality on project management

Good to Have

• Experienced in analog layout
• Knowledge of Script Programming
• Knowledge of SKILL Programming
• Experience in memory compiler

The descriptions are for layout engineers for our Library Group. Library Group is a part of Central Engineering Group.

In Library Group, we focus on circuit design for memory, I/O (Input/Output), and Standard Cells.

Requirements:

• Strong layout knowledge with a minimum of 2 to 3 years of experience
• Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
• Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm,2nm etc
• Experienced in digital (standard cell, memory, I/O) layout
• Experienced in analog layout is also a plus

Job Description:

• Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout
• Schedule time-line & layout floor-planning
• Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
• Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set (Mem):

• Strong experience in memory layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration in CMOS process.
• Experienced in Cadence Layout tools VIRTUOSO (XL,VXL or EXL), and CALIBRE verification tools.
• Good experience in Floor-planning, hierarchy layout and chip integration.
• Knowledge of Script Programming and SKILL Programming would be a plus.
• Able to lead or train a team of junior engineers
• Good knowledge on memory layout topology.
• Experience in memory compiler will be a plus.
• Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
• Self-reliant, with ability to work independently as well as a team.
• Good leadership quality on project management.