Lead Product Engineer

4 Months ago • 1-3 Years • $114,800 PA - $213,200 PA

Product Management

Job Description

As a Product Engineer in the Digital and Signoff Group at Cadence, you will work with R&D, the application team, and product marketing to influence the development of software tools for advanced chip design platforms. You will be a source of technical place and route expertise for Cadence customers and R&D. You will debug customer problems, propose solutions, and run design benchmarks. The responsibilities include supporting Cadence products in the Digital and Signoff team, tracking and debugging customer issues, and developing flows and solutions. The role requires a deep understanding of ASIC design methodologies and experience with timing closure and PPA optimization.

Must Have:

BS in EE with 3+ years experience or MS in EE with 1+ years experience
Strong understanding of VLSI physical design and timing analysis
Experience with industry standard EDA tools
Energetic team player with a passion for problem solving
Strong analysis skills with a track record to prove it
Strong communication skills (verbal and written)
Automation skills using Perl, Tcl and shell scripting

Add these skills to join the top 1% applicants for this job

communication

team-player

shell

perl

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with R&D, application team, product marketing team to influence the development of software tools for advanced chip design platforms.

As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.

You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.

You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.

You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach. You are an excellent communicator.

Position Responsibilities:

Support Cadence products in the Digital and Signoff team.

Track and debug customer issues and work with R&D and release team on issue resolution.

Run design benchmarks and develop flows and solutions for customers.

Position Requirements:

BS in EE with 3+ year experience or MS in EE with 1+ years of experience in Digital Implementation, either as a design engineer or as a product engineer

Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff.

Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.

Energetic team player with a passion for problem solving

Strong analysis skills with a track record to prove it

Strong communication skills (verbal and written)

Automation skills using Perl, Tcl and shell scripting

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.