Senior Product and Test Engineer

Cerebras Systems is seeking a Senior VLSI Product and Test Engineer with over 10 years of expertise in semiconductor testing, with a specialized focus on wafer-scale and large-scale AI/ML accelerator testing. This role involves driving test program development for wafer-scale processors, implementing innovative test strategies for massive parallel processing units, IOs, and memories, and optimizing test programs for yield. The successful candidate will work closely with teams across chip design, fabrication, validation, production, and manufacturing to deliver end-to-end solutions for Cerebras’s Wafer Scale Engine.

Must Have

• Design and develop comprehensive test programs for wafer-scale processors and large-scale AI/ML accelerator chips.
• Implement sophisticated DFT strategies for wafer-scale designs, including hierarchical scan chains and distributed BIST.
• Create scalable test methodologies for testing hundreds to thousands of processing cores on a single wafer, with distributed SRAM.
• Develop fault isolation techniques for identifying defective cores/tiles within wafer-scale processors.
• Implement efficient wafer-level test flows that can handle massive parallelism and complex interconnect structures.
• Work with DFT engineers, silicon architects/designers, performance engineers, and software engineers to enhance testability.
• Refine test programs for di/dt, V-F characterization space, current and temperature limits.
• Optimize test programs for testing multiple die simultaneously while maintaining test quality.
• Develop innovative approaches for power delivery and thermal management during wafer-level testing.
• Develop test strategies for wafer-scale integration-testing, yield optimization, redundancy, and fault tolerance verification.
• Analyze spatial defect patterns across wafer-scale devices and implement corrective actions.
• 10+ years of hands-on experience in semiconductor test engineering with a focus on large-scale integration.
• Proven track record in wafer-scale testing, AI/ML accelerator testing, or large parallel processor/GPUs with SRAM, DDR-DRAM, HBM.
• Expert-level Advantest 93K experience with Teradyne as an alternative.
• Experienced in advanced interconnect testing (mesh networks, NoC, high-speed serial links).
• Expertise in High-Speed Serdes testing at ATE, package, and system level.
• Experience in handling analog blocks in large digital ASICs.
• Expertise in load-board and probe-card specification, design, development, and debug for advanced DFT implementation.
• Test program development and optimization, production test debugging, and yield improvement.
• Working knowledge of git repositories, GitHub, git actions/Jenkins, merge and release flows to streamline test and release.

Good to Have

• Proficiency in programming languages: C/C++, Python, Perl for large-scale data analysis.
• Experience with advanced test data analysis tools and machine learning techniques for yield optimization.
• Familiarity with advanced packaging technologies for wafer-scale systems (TSV, advanced interconnects).
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across manufacturing steps.

Perks & Benefits

• Build a breakthrough AI platform beyond the constraints of the GPU.
• Publish and open source their cutting-edge AI research.
• Work on one of the fastest AI supercomputers in the world.
• Enjoy job stability with startup vitality.
• Simple, non-corporate work culture that respects individual beliefs.

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.

Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring our commitment to transforming AI applications across various fields. In August, we launched Cerebras Inference, the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services.

We are seeking a highly experienced Senior VLSI Product and Test Engineer with 10+ years of expertise in semiconductor testing, with a specialized focus on wafer-scale and large-scale AI/ML accelerator testing. The successful candidate will drive test program development for wafer-scale processors, drive innovative test strategies for massive parallel processing units, IOs, and memories.

In this exciting role, you will be responsible for ATE strategy for future generations of Cerebras’s Wafer Scale Engine (WSE). Suitable candidate will have depth in testing, characterization of silicon defects, failure modes, and experience delivering end-to-end solutions working closely with teams across chip design, fabrication, validation, production, and manufacturing.

Key Responsibilities

• Design and develop comprehensive test programs for wafer-scale processors and large-scale AI/ML accelerator chips
• Implement sophisticated DFT strategies for wafer-scale designs, including hierarchical scan chains and distributed BIST
• Create scalable test methodologies for testing hundreds to thousands of processing cores on a single wafer, with distributed SRAM
• Develop fault isolation techniques for identifying defective cores/tiles within wafer-scale processors
• Implement efficient wafer-level test flows that can handle massive parallelism and complex interconnect structures such as mesh networks, on-chip NoC, and die-to-die communication
• Work with the DFT engineers, silicon architects/designers, performance engineers, and software engineers to enhance the testability of Wafer Scale Engines.
• Work refining test programs for di/dt, V-F characterization space, current and temperature limits
• Optimize test programs for testing multiple die simultaneously while maintaining test quality
• Develop innovative approaches for power delivery and thermal management during wafer-level testing
• Develop test strategies for wafer-scale integration-testing, yield optimization, redundancy, and fault tolerance verification
• Analyze spatial defect patterns across wafer-scale devices and implement corrective actions

Required Skills & Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of hands-on experience in semiconductor test engineering with a focus on large-scale integration
• Proven track record in wafer-scale testing, AI/ML accelerator testing, or large parallel processor/GPUs with SRAM, DDR-DRAM, HBM
• Expert-level Advantest 93K experience with Teradyne as an alternative
• Experienced in advanced interconnect testing (mesh networks, NoC, high-speed serial links)
• Expertise in High-Speed Serdes testing at ATE, package, and system level
• Experience in handling analog blocks in large digital ASICs
• Expertise in load-board and probe-card specification, design, development, and debug for advanced DFT implementation that comprises boundary scan, scan, BIST, ATPG, and functional tests
• Test program development and optimization
• Production test debugging, and yield improvement
• Good interpersonal skills with the ability & desire to work as a standout teammate and problem solver
• Proven track record of working cross-functionally, learning fast, and driving issues to closure
• Working knowledge of git repositories, GitHub, git actions/Jenkins, merge and release flows to streamline test and release

Preferred

• Proficiency in programming languages: C/C++, Python, Perl for large-scale data analysis
• Experience with advanced test data analysis tools and machine learning techniques for yield optimization
• Familiarity with advanced packaging technologies for wafer-scale systems (TSV, advanced interconnects)
• Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
• Knowledge of chip defect profiles and mitigation strategies across manufacturing steps

Location:

North America based. Sunnyvale, up to 20% travel may be needed.

The base salary range for this position is $175,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

1. Build a breakthrough AI platform beyond the constraints of the GPU.

2. Publish and open source their cutting-edge AI research.

3. Work on one of the fastest AI supercomputers in the world.

4. Enjoy job stability with startup vitality.

5. Our simple, non-corporate work culture that respects individual beliefs.

Read our blog: Five Reasons to Join Cerebras in 2025.

Apply today and become part of the forefront of groundbreaking advancements in AI!

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Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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