Sr Principal Product Validation Engineer
1 Year ago • All levels
Product Management
Job Description
Cadence seeks a Sr Principal Product Validation Engineer with expertise in HDLs, EDA tools, and functional verification of complex digital systems. Strong experience in SystemVerilog, C++, UVM, and knowledge of protocols like PCIe, USB3/4, DP is a plus. Join a team developing impactful technology.
Good To Have:
- Process Automation
- Scripting
- SoC Verification
- PCIe, USB3/4, DP
Must Have:
- HDLs (Verilog, VHDL)
- EDA Tools
- SystemVerilog, C++, UVM
- Functional Verification
Perks:
- Impactful Technology
- Leadership Development
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
- Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
- Experience in process automation with scripting.
- Experience with SystemVerilog, C++, UVM.
- Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
- Experience designing and implementing complex functional verification environments is required.
- Knowledge of protocols like PCIe, USB3/4, DP an added advantage.
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