IC Packaging Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a candidate to be part of its Technical Field Organization in the Silicon Package Board group, with a focus on IC Package design solutions. If you like to develop solutions for challenging problems at top tier customers in an innovative and fast paced environment, using state of the art technology, this is a great opportunity.

The candidate will work closely with our customers in supporting technical campaigns by delivering workshops, product demonstrations, knowledge transfer, training delivery, and onsite support. The candidate will have expert knowledge of the Cadence tool set in the context of multiple flows including IC Packaging, high speed design, signal integrity and electrical constraints definition. Design experience and industry knowledge of current IC Packaging Design and manufacturing processes is required. Knowledge of advanced IC packaging flows preferred.

The candidate needs to have the ability to analyze customer's environment and evaluate appropriate solutions. Be knowledgeable and aware of competitive technologies. Anticipates technical issues and develops creative solutions before they become a problem. Takes technical lead on wide range of projects. Ability to understand IC package related issues, and work with peers and other business groups.  Able to work on-site with customers without supervision. Able to communicate effectively with Cadence R&D, Product Engineering, Marketing and with customers. Understands customer success criteria and is committed to ensuring customer success.

The Position Requirements are:

• Bachelor’s degree in Electrical or Electronics Engineering with 5 to 10 years related experience. Master’s preferred.   
• Candidate should have experience in Cadence Allegro platform tools including: Allegro Package Designer (APD+), Allegro PCB Editor, constraint management, routing, HDI.
• Design experience and industry knowledge of advanced IC Package design flows. (Ex: InFO, FOWLP, CoWoS, etc…)
• Electromagnetics, and RF related to IC Package Design is required. 
• In-depth knowledge of EDA industry, Signal Integrity, Power Integrity is a plus.
• Experience with data management applications, and Cadence Allegro SKILL, Tcl is desirable. 
• Must have excellent English written and verbal communication skills. 
• Ability to present and clearly articulate solutions individually and in front of medium to large groups is required.

The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.