Physical Design SoC Lead

Job Description:

As a Physical Design SoC Lead, you will be responsible for design and implementation of a significant portion of a custom Xeon SoC. Your role will be to plan and lead cluster and partition development from RTL to TI-ready GDS. You will work closely with silicon architects, RTL design engineers, internal/external IP vendors, and DFT/DFD teams, getting exposure to all aspects of product development. This role requires strong partnership between you and SoC Physical Design Manager to drive execution through deep technical understanding and ability to highlight critical challenges. You will also be responsible for working with and leading a team of more junior engineers in executing partitions within the same cluster. You will be expected to strongly contribute to methodology and flow definition used across the physical design team in order to enable the team to meet project schedules. You will drive all aspects of the physical design flow, including:

• Floorplanning, synthesis, place and route, and clock tree synthesis
• Static timing analysis, power and clock distribution, and noise analysis
• Design closure and sign-off for TI, including:
• Formal equivalence verification
• Convergence to power and performance goals
• Reliability verification
• Layout verification / DRC
• Electrical rule checking

Key Responsibilities:

• Plan the physical implementation of a logical SoC cluster
• Work across architecture, IP, RTL, DFT/DFD and other teams as needed to understand design requirements and dependencies
• Drive timing closure and PPA optimization
• Develop and enhance physical design methodologies and automation flows
• Mentor and grow technical talent across the organization
• Act as a domain expert, influencing technical direction across Intel and the broader industry
• Deliver design to schedule commitments

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

MINIMUM QUALIFICATIONS

The candidate must have a Bachelor's degree in Computer or Electrical Engineering or related field with 9+ years of industry experience -OR- a Masters degree in Computer or Electrical Engineering with 6+ years of industry experience and expertise in synthesis, place and route static timing analysis using Primetime tools, DFT flows, and low power design

PREFERRED QUALIFICATIONS

Good knowledge of Fusion Compiler and Prime Time. Experience as technical leader of SOC/ASIC designs responsible for physical convergence, planning, and execution from synthesis to GDS. Proven track record of strong partnership and collaboration with managers, RTL design and other partner teams. The ideal candidate will also have strong written and verbal communication skills and the ability to drive a team.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$177,200.00-$250,160.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.

The application window for this job posting is expected to end by 10/15/2025