Post Silicon Electrical Validation Intern

6 Minutes ago • All levels
Testing

Job Description

This on-site Post Silicon Electrical Validation Intern role in San Jose, CA, within the Cadence IP group, involves collaborating with the engineering team to validate the electrical performance of internal silicon test chips. The intern will debug silicon issues by working with analog and digital design teams and releasing high-quality characterization reports. The role emphasizes cross-functional collaboration to ensure product reliability and functionality, contributing to bleeding-edge SERDES designs like PCIe Gen7 and 224Gbps Ethernet.
Good To Have:
  • Prior experience in the hardware semiconductor or electronics industry
  • Experience with script-based test automation in Perl, Python, or other scripting tools
Must Have:
  • Strong motivation for driving electrical testing efforts for identifying silicon issues and being involved in debug efforts
  • Very good fundamentals in analog electronics, digital electronics, negative feedback theory, stability and control systems theory
  • Strong analytical and problem-solving skills
  • Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering
  • Completion of at least three years of undergraduate coursework
  • Excellent written and verbal communication skills
  • Ability to work collaboratively in a team environment

Add these skills to join the top 1% applicants for this job

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Company Description

Cadence is a leader in electronics and system design, leveraging over 30 years of computational software expertise. The company’s Intelligent System Design strategy enables creating software, hardware, and IP that turn design concepts into reality. Cadence's customers include the world’s leading companies who deliver extraordinary electronic products across various dynamic market applications such as hyperscale computing, 5G communications, automotive, aerospace, and healthcare. Recognized by Fortune magazine for eleven consecutive years, Cadence is one of the 100 Best Companies to Work For.

Role Description

This is an on-site role for a Post Silicon Electrical Validation Intern based in San Jose, CA, in the Cadence IP group. The intern will be responsible for collaborating with the engineering team in validating the electrical performance of our internal silicon test chips, debugging silicon issues by collaborating with the analog and digital design teams and releasing high quality characterization reports. The role involves collaborating with cross-functional teams to ensure the reliability and functionality of the product.

Why Cadence?

Cadence is at the forefront when it comes to the development of bleeding edge technology SERDES designs such as PCIe Gen7, 224Gbps Ethernet amongst other protocols and joining us gives you a golden opportunity to partner in our progress.

Qualifications

  • The candidate is expected to be strongly motivated by the prospect of driving electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same.
  • Very good fundamentals in analog electronics, digital electronics, negative feedback theory, stability and control systems theory
  • Strong analytical and problem-solving skills
  • Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering
  • Completion of at least three years of undergraduate coursework.
  • Excellent written and verbal communication skills
  • Ability to work collaboratively in a team environment
  • Prior experience in the hardware semiconductor or electronics industry is a plus
  • Experience with script-based test automation in Perl, Python, or other scripting tools is a plus

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