Senior Physical Design Clock Distribution Engineer

41 Minutes ago • 2 Years + • $161,230 PA - $303,140 PA

Network Engineering

Job Description

Intel is seeking a Senior Physical Design Clock Distribution Engineer to join the Silicon Engineering Group (SIG). This role involves defining and developing physical clock architecture, driving clocking designs, creating methodologies, and implementing solutions for IPs or SoCs. Responsibilities include building simulation models, driving physical implementation, conducting clock analysis, and supporting power grid methodologies. The engineer will interact with architecture and design teams to meet clocking requirements and optimize for power and performance. Strong collaboration and communication skills are essential for this role.

Good To Have:

Experience in Fusion Compiler and clock distribution tools such as Clock Builder.
Experience as technical leader of SOC/ASIC designs responsible for planning design and physical convergence of SoC clock distribution.

Must Have:

Define and develop physical clock architecture.
Drive clocking designs and create clocking methodologies and guidelines for IPs or SoCs.
Design new clock modules and circuit solutions.
Implement solutions that meet security and safety compliance for IP or SoC clocking.
Define SoC or subsystem level clocking targets and drive design teams.
Build simulation models, drive physical implementation, conduct clock analysis, and support power grid methodologies.
Create scalable flows for clocking infrastructure.
Interact with architecture and IP/SoC design teams to understand clocking requirements.
Bachelor's Degree with 6+ years, Master's with 4+ years, or PhD with 2+ years of relevant experience.
2+ years of experience in synthesis, place and route static timing analysis using Primetime tools, DFT flows, and low power design.

Perks:

Competitive pay
Stock options
Bonuses
Health benefits
Retirement programs
Vacation

Add these skills to join the top 1% applicants for this job

communication

game-texts

Job Description:

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

We Are the Silicon Engineering Group (Sig). We provide silicon for Data Center & AI while delivering leadership products and delighting our customers.

Who You Are

Your responsibilities may include but not be limited to:

Defines and develops physical clock architecture, drives clocking designs, and creates clocking methodologies and guidelines for IPs or SoCs.
Designs new clocks modules and circuit solutions and implements solutions that meet security and safety compliance for IP or SoC clocking.
Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required.
Build simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation.
Creates scalable flows for clocking infrastructure for better performance and power in the design.
Interacts with architecture and IP/SoC design teams to understand clocking requirements and help them in deciding the right clock distribution methodology based on power and performance requirements.
Proven track record of strong partnership and collaboration with managers, RTL design, architects and other partner teams.
The ideal candidate will also have strong written and verbal communication skills and the ability to drive a team.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must have a Bachelor's Degree in Computer or Electrical Engineering or related field with 6+ years of relevant experience -OR- a Master’s Degree in Computer or Electrical Engineering or related field with 4+ years of relevant experience -OR- PhD in Computer or Electrical Engineering with 2+ years of relevant experience
2+ years of experience in synthesis, place and route static timing analysis using Primetime tools, DFT flows, and low power design

Preferred Qualifications

Experience in Fusion Compiler and clock distribution tools such as Clock Builder.
Experience as technical leader of SOC/ASIC designs responsible for planning design and physical convergence of SoC clock distribution.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Texas, Austin

Additional Locations:

US, California, Santa Clara, US, Massachusetts, Beaver Brook

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-303,140.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.