Job Description
As a Senior SOC DFT Engineer, you will be responsible for developing logic design, RTL coding, simulation, and providing DFT timing closure support. This role involves generating test content for manufacturing, participating in architecture definition of DFT features, and developing HVM content for rapid bring-up on ATE. You will optimize logic to meet power, performance, area, timing, and test coverage goals, ensuring design integrity and high-quality integration of DFT blocks into IP and SoC. Collaboration with post-silicon and manufacturing teams for verification and debug is also key.
Good To Have:
- Experience with advanced test techniques such as DFT for low-power designs.
- Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test).
- Knowledge of Python or other scripting languages for automation.
- Experience with failure analysis, yield improvement and test cost optimization methodologies.
- Experience with SOC (System on Chip) or complex multi-chip designs.
Must Have:
- Develop logic design, RTL coding, simulation, DFT timing closure support, and test content generation.
- Participate in defining architecture and microarchitecture features of DFT for block, subsystem, and SoC.
- Develop HVM content for rapid bring-up and production on automatic test equipment (ATE).
- Apply strategies, tools, and methods to write and generate RTL and structural code for DFT integration.
- Optimize logic to meet power, performance, area, timing, test coverage, DPM, and test time goals.
- Review verification plans and drive verification of DFT design.
- Integrate DFT blocks into functional IP and SoC, supporting SoC customers.
- Collaborate with post-silicon and manufacturing teams for verification and debug.
- Drive high test coverage through structural and specific IP tests.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
- 5+ years of experience in DFT, SOC design, or related semiconductor design areas.
- Strong knowledge of DFT techniques, including BIST, boundary scan, JTAG, and fault simulation.
- Experience with EDA tools for DFT (e.g., Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, ATPG).
- Proficiency in hardware description languages such as VHDL, Verilog, or System Verilog.
- Expertise in automated test generation and analysis tools.
- Strong problem-solving skills with the ability to troubleshoot complex testability issues.
- Experience with RTL design and verification processes.
- Excellent communication and teamwork skills.
- Ability to analyze, review, and optimize existing DFT strategies.
- Familiarity with semiconductor manufacturing processes and test flows.
Job Details:
Job Description:
- Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including BSCAN).
- Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, BSCAN, proc monitors, in system test/BIST).
- Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
- Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block. Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
- Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
- 5+ years of experience in DFT, SOC design, or related semiconductor design areas. Strong knowledge of DFT techniques, including BIST, boundary scan, JTAG, and fault simulation.
- Experience with EDA tools for DFT (e.g., Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, ATPG).Proficiency in hardware description languages such as VHDL, Verilog, or System Verilog.
- Expertise in automated test generation and analysis tools. Strong problem-solving skills with the ability to troubleshoot complex testability issues. Experience with RTL design and verification processes.
- Excellent communication and teamwork skills to collaborate with multi-disciplinary teams. Ability to analyze, review, and optimize existing DFT strategies for design and test coverage. Familiarity with semiconductor manufacturing processes and test flows.
Preferred Qualifications :
- Experience with advanced test techniques such as DFT for low-power designs. Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test), and others.
- Knowledge of Python or other scripting languages for automation.
- Experience with failure analysis, yield improvement and test cost optimization methodologies.
- Experience with SOC (System on Chip) or complex multi-chip designs requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
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