ASIC VERIFICATION ENGINEER

This role involves working on cutting-edge CSG Switches and contributing to the AI Network Infrastructure Ecosystem by defining new features. You will develop and maintain verification environments using SystemVerilog/UVM, understand end-to-end specifications, and collaborate closely with architecture, micro-architecture, and design teams for test plan development. The position also covers coverage closures, gate-level simulations, and the entire end-to-end verification cycle.

Must Have

• 8+ years of verification experience
• Wide exposure to chip level (SoC) verification
• SystemVerilog/UVM methodology
• Expertise in Co-Simulations (HW/SW) Flow and debugs
• Experience in GLS, Coverage Driven Methodology, ATE
• Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper

Good to Have

• Exposure to any one of the scripting languages - Perl or Python or SED/Awk
• Knowledge of networking protocols (L2/L3/L4, 1588TS, UEC)
• Expertise in High Speed bus protocols (PCIe, Ethernet, AXI4.0)
• Exposure to Chip level Interconnect/Testability Functions (JTAG, I2C, PLLs)
• Exposure to Test Bench Accelerators /Emulation Platforms

Job Description:

What You can Expect -

• Work on Latest cutting edge CSG Switches.
• To be part of the team working on defining many Firsts for the AI Network Infrastructure Ecosystem.
• Develop and maintain verification Environment in Mix of SV/UVM.
• Understanding of the End to End spec along with Network & System topology.
• Closely working with Arch/uArch/Design team for Test Plan development and closure of the feature set across Blocks/Top level.
• Coverage Closures, Gate Level Simulations along with end to end verification cycle.

What we are looking for -

• Bachelor's/Masters/PhD with Verification experience of 8+ years
• Wide exposure to chip level (SoC) verification and SystemVerilog/UVM methodology a MUST
• Exposure to any one of the scripting languages - Perl or Python or SED/Awk
• Expertise in Co-Simulations (HW/SW) Flow and debugs
• Knowledge of networking protocols(L2/L3/L4, 1588TS, UEC) desired but not necessary.
• Expertise in the High Speed bus protocols desired - PCIe, Ethernet, AXI4.0
• Exposure the Chip level Interconnect/Testability Functions - JTAG, I2C, PLLs etc
• Experience in GLS, Coverage Driven Methodology, ATE
• Good exposure in Simulation tool usage for simulation (VCS) and waveform debug(Verdi) and formal tools like Jasper.
• Exposure to Test Bench Accelerators /Emulation Platforms.