CAD Engineer - Timing for Gate-Level Flows & Methodologies
3 Months ago • All levels
Level Design
Job Description
As a member of the STA CAD team, this role involves developing, maintaining, and enhancing existing gate-level STA flows for Apple silicon designs. Responsibilities include working with design teams to understand and debug issues related to constraints, flow scripts, and timing closure. The engineer will facilitate and drive STA methodology changes to improve efficiency, productivity, and silicon timing correlation. This includes developing and maintaining scripts and methods for timing analysis and power reduction, as well as developing and supporting methodologies, tools, and flows used in the verification of timing constraints and driving best practices across design teams. The role also entails analysis of timing paths to identify key issues, including post-silicon timing debug, and close collaboration with EDA vendors to develop and incorporate new capabilities to solve technical problems.
Must Have:
- Develop, maintain, and enhance gate-level STA flows
- Debug constraints, flow scripts, and timing closure issues
- Drive STA methodology changes for efficiency
- Develop scripts for timing analysis and power reduction
- Support timing constraint verification methodologies and tools
- Analyze timing paths for key issues
- Collaborate with EDA vendors for new capabilities
As a member of our STA CAD team, you will:
• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems
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