CAD Engineer - Timing for Gate-Level Flows & Methodologies

As a member of the STA CAD team, this role involves developing, maintaining, and enhancing existing gate-level STA flows for Apple silicon designs. Responsibilities include working with design teams to understand and debug issues related to constraints, flow scripts, and timing closure. The engineer will facilitate and drive STA methodology changes to improve efficiency, productivity, and silicon timing correlation. This includes developing and maintaining scripts and methods for timing analysis and power reduction, as well as developing and supporting methodologies, tools, and flows used in the verification of timing constraints and driving best practices across design teams. The role also entails analysis of timing paths to identify key issues, including post-silicon timing debug, and close collaboration with EDA vendors to develop and incorporate new capabilities to solve technical problems.