Internship: Phase Lock Loop Modeling with Matlab Tool (F/M)

This internship focuses on modeling Phase Locked Loop (PLL) systems using Matlab/Simulink for NXP's Secure Connectivity Edge Business Line in Caen, which develops integrated circuits for NFC and Bluetooth applications. The intern will be responsible for modeling various PLL types (Type I and Type II) in both time and Laplace domains to support engineering development tasks.

Must Have

• Master's degree in analog or digital electronics or second year of engineering school
• Knowledge of PLL, control systems, and signal processing
• Proficiency in Matlab/Simulink and C programming
• Good level of English and French

Context:

The Business Line SCE (Secure Connectivity Edge), based in CAEN, develops integrated circuits in sub-nanometer processes for NFC, Bluetooth applications.

In this context, we need to develop tools to help engineers in their development task, and in particular, to model different types of PLL (Phase Locked Loop) in Matlab code / Simulink environment.

We are looking for candidates, specialized in analog or digital electronics and signal processing for a 2/3-month Internship in Caen, starting beginning of 2026.

Your Responsibilities:

You will be in charge of modeling different types of PLL with Matlab (Type I and Type 2), in the time domain and the Laplace domain.

Your Profile:

Education level: Master’s degree in analog or digital electronics, second year of engineering school (Bac + 4 minimum)

Experience / Knowledge: Analog or digital electronics, signal processing, PLL, control loops

Knowledge in language: Matlab/Simulink, C

A good level of English & French is required, working in an international multi-site team.