Standard Cell Library Design Engineer

Broadcom's Central Engineering Group builds the Foundation IP that powers Broadcom's leading silicon product families. This role involves designing, developing, and delivering standard cell library foundation IP. Key responsibilities include transistor-level standard cell design, circuit simulation and analysis, generating and verifying library EDA models, running regression and quality checks, and supporting design teams.

Must Have

• Digital or mixed-signal circuit design knowledge
• Understanding of cell layout or physical design
• Understanding of FinFet, RibbonFet/GAA process nodes
• Understanding of verilog, lef, liberty and other industry standard EDA models
• Familiarity with EDA tools used in FE (Extraction, sims, char) and BE (Verification, STA, P&R)
• Bachelor's in Electrical/Electronic or Computer Engineering and 5+ years of related experience OR Master's and 3+ years of related experience OR PhD with no experience
• Singapore Citizen/PR only

Good to Have

• Experience with .lib syntax including NLDM/CCS/LVF
• Experience with Virtuoso, Cadence Skill programming, scripting using Unix, Perl, TCL or Python
• Excellent written and verbal communication skills
• Ability to collaborate and work within and across teams

Job Description:

Broadcom's Central Engineering Group builds the Foundation IP that powers Broadcom's leading silicon product families. In this position, the successful candidate will be part of the team responsible for the design, development and delivery of standard cell library foundation IP

Job Responsibilities:

• Design standard cells at transistor level
• Simulate and analyze circuit designs
• Generate and verify library EDA models
• Run regression and quality checks on library deliverables
• Interface with design teams to support their requirements

Key Requirements:

• Digital or mixed-signal circuit design knowledge
• Understanding of cell layout or physical design
• Understanding of FinFet, RibbonFet/GAA process nodes
• Understanding of verilog, lef, liberty and other industry standard EDA models
• Familiarity with EDA tools used in FE (Extraction, sims, char) and BE (Verification, STA, P&R)
• Experience with .lib syntax including NLDM/CCS/LVF is a plus
• Experience with Virtuoso, Cadence Skill programming, scripting using Unix, Perl, TCL or Python is strongly desired

Qualifications & Experience:

• Bachelor's in Electrical/Electronic or Computer Engineering and 5+ years of related experience / Candidates with Masters and 3+ years of related experience / PhD in related field of studies with no experience
• Singapore Citizen/PR only

Additional Qualifications:

• Excellent written and verbal communication skills
• Collaborate and work within and across teams