The IC Layout Designer will collaborate with IC Design Engineers across three design sites, including the USA, UK, and Switzerland, to translate circuit schematics into physical layouts. This role involves working with technology engineers to implement circuit components such as transistors, resistors, capacitors, and test structures within the physical layout. The designer will also be responsible for verifying the completed physical layout using CAD tools like Cadence Layout and Schematic editor and Mentor Calibre DRC and LVS, and for preparing and taping out the verified layout database to the mask shop.