Infra NOC (RTL)Design Engineer-Staff/Sr Staff

Qualcomm is seeking a NoC design lead for the BDC infrastructure core team. This role involves specifying, designing, and implementing interconnects and related IPs, collaborating with SoC, verification, and physical design teams. Responsibilities include ensuring interconnect performance, correlating pre-silicon and post-silicon design assumptions, and micro-architecting debug hooks for silicon issues. The engineer will define and resolve complex problems, manage diverse teams, and contribute to product competitiveness and business objectives through design and problem-solving.

Must Have

• 8+ years of experience in IP/SoC design and micro-architecture
• Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
• Good knowledge of Digital Design and RTL development
• Hands-on experience with SoC Design, Verilog RTL coding
• Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization
• Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug
• Working knowledge of Lint, CDC, PLDRC, CLP etc
• Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
• Ability to manage SoC dependencies, planning and tracking of all front-end design related tasks
• Experience driving project milestones across design, verification and physical implementations
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of experience (or Master's with 5+, PhD with 4+)

Good to Have

• Automation
• CMOS
• Circuits

Perks & Benefits

• World-class health benefit options
• Programs to build and prepare for a financially secure future
• Self and family resources for emotional/mental strength and resilience
• Wellbeing programs and resources to Live+Well and Work+Well
• Continuous learning and development programs
• Tuition reimbursement
• Mentorships

General Summary:

• NoC design lead and is part of BDC infrastructure (NoC/Interconnect) core team
• Responsible for specification, design and implementation of interconnect and related IP’s
• Actively work with SoC team, verification team, physical design team, SoC Floorplan, core teams and various other interconnect teams in various other sites
• Partner with SoC performance team ensuring Interconnect meeting all performance requirement, and with silicon validation team to co-relate pre-silicon and post silicon design assumptions
• Responsible for micro-architecting all relevant debug hooks in NoC Infrastructure to help root cause silicon issues
• Looks beyond existing methodologies and own discipline to define and resolve complex problems
• Manages large, potentially diverse teams of managers and/or senior professionals
• Provides input to functional or departmental strategy
• Create an impact on product competitiveness, roadmap and business objectives through Design/DV/Problem Solving
• Lead by example on customer problem solving related to NoC/Interconnect

Minimum Qualifications:

• 8+ years of solid experience in IP/SoC design and micro-architecture
• Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
• Good knowledge of Digital Design and RTL development
• Hands-on experience with SoC Design, Verilog RTL coding
• Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.
• Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug
• Working knowledge of Lint, CDC, PLDRC, CLP etc
• Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification
• Manage SoC dependencies, planning and tracking of all front-end design related tasks
• Driving project milestones across the design, verification and physical implementations
• Should possess effective communication and leadership skills
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR

• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.