CPU Physical Design Automation Engineer

Intel is seeking a CAD Physical Design Engineer for the E-core CPU team. This role involves developing, debugging, and supporting tools, flows, and methodologies for backend physical design, including RTL2GDS standard cell level design techniques. The engineer will analyze synthesis, place and route, floor planning, and signoff for timing, power, and reliability, working closely with design teams and EDA vendors to create high-speed, low-power synthesizable CPUs. Excellent communication skills are essential.

Must Have

• Develop, debug, and support tools, flows, and methodologies covering backend physical design methodologies and flow automation.
• Perform analysis of synthesis, place and route, floor planning or signoff for static timing analysis, formal equivalence verification, power consumption, electrical rule checking, and circuit reliability.
• Work closely with design teams to understand and debug tool issues and constraints.
• Bachelor's Degree in Computer Engineering and/or Electrical Engineering and 4+ years of relevant working experience OR Master's Degree in Computer Engineering and/or Electrical Engineering and 3+ years of experience.
• 1+ years of experience in hardware design and engineering, such as VLSI, design automation algorithms, and transistor-level design.
• 1+ years' experience with Python, Perl, and/or Tcl scripting languages.

Good to Have

• 1+ years of relevant working experience in microprocessor or other high speed design backend design.
• 1+ years of experience using industry standard Engineering Design Automation (EDA) VLSI tools/flows from vendors such as Synopsys, Cadence and/or Mentor Graphics for performing synthesis, place-and-route, extraction, timing/power analysis and functional verification.
• Experience with timing closure methodology for worst-case corner (static timing analysis / STA, statistical variation analysis, spice circuit simulation, ERC, noise analysis flows, cross talk, OCV effects, budget constraints).

Perks & Benefits

• Competitive pay
• Stock
• Bonuses
• Health benefits
• Retirement programs
• Vacation
• Hybrid work model

Job Description:

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world-changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

The E-core CPU team is powered by some of the brightest and most innovative minds in the industry and we need you. Intel has a vision to create and extend computing technology to connect and enrich the lives of every person. We are designing future generations of high-performance E-core CPUs using the most advanced and innovative process technologies. If you are looking to grow and develop your skillsets while being surrounded by highly motivated and knowledgeable teammates, then this is the organization for you.

E-Core CPUs are the industry-leading performance-per-watt CPU that helps:

• Power the latest Intel laptops, desktops, and high-end gaming platforms.
• Drive 5G communications by serving as the base station that delivers essential data from your electronic devices across the world at maximum bandwidth.
• Create Artificial Intelligence (AI) and machine learning devices.
• Enable a full virtual learning experience for students using the latest Google Chromebooks.

Who You Are

As a CAD Physical Design Engineer in the E-core CPU group, you will be responsible for:

• Developing, debugging, and supporting tools, flows, and methodologies covering backend physical design methodologies and flow automation for high-performance blocks and full chip level using RTL2GDS standard cell level design techniques.
• Performing analysis of either synthesis, place and route, floor planning or signoff for static timing analysis on timing paths, formal equivalence verification, power consumption, electrical rule checking, and circuit reliability to identify key issues.
• Working closely with design teams to understand and debug tool issues and constraints.
• Working with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.
• Creating documentation and helping with guidelines/specs.
• Communicating with other team members to solve problems and following solutions through to completion. Excellent verbal and written English communication skills.

Qualifications:

You must possess the minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience.

Minimum Qualifications

• Bachelor's Degree in Computer Engineering and/or Electrical Engineering and 4+ years of relevant working experience OR Master's Degree in Computer Engineering and/or Electrical Engineering in Computer Engineering and/or Electrical Engineering and 3+ years of experience
• 1+ years of experience in hardware design and engineering, such as VLSI, design automation algorithms, and transistor-level design
• 1+ years' experience with Python, Perl, and/or Tcl scripting languages.

Preferred Qualifications

• 1+ years of relevant working experience in microprocessor or other high speed design backend design.
• 1+ years of experience using industry standard Engineering Design Automation (EDA) VLSI tools/flows from vendors such as Synopsys, Cadence and/or Mentor Graphics for performing synthesis, place-and-route, extraction, timing/power analysis and functional verification.
• Experience with timing closure methodology for worst-case corner (static timing analysis / STA, statistical variation analysis, spice circuit simulation, ERC, noise analysis flows, cross talk, OCV effects, budget constraints)

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Texas, Austin

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US: 121,050.00 USD - 197,230.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.