About the job
Responsibilities- Lead a SoC PD team and own the RTL2GDSii implementation of a complex ARM architecture based SoC right upto tapeout
- Manage a high impact PD team and take accountability for their timely deliverables
- Drive physical design excellence and beat PPA goals with methodology improvements on implementation tools, flow, and methodology by partnering with EDA counterparts
- Interface with architecture, RTL and DFT teams to understand IP and partition level architectures and drive physical aspects early in design cycle.
- Own and execute on power management aspects of implementation to improve active and leakage power goals
- Own timing constraints for partitions and at SoC level and ensure critical IO interfaces are also met
- Review all technical deliverables from team members and guide team members to meet quality and schedule
- Responsible for resolution of physical design related cross functional issues and dependencies across RTL integration, Verification , DFT and related analysis and debugs
- Own and ensure closure of timing, physical & electrical verification as well as signoff closure for all the partitions and for the full SoC
- Drive and motivate the team to constantly innovate on flows and methodologies that will enable better PPA for the design
- Actively collaborate across WW PD teams and across EP to leverage and share best practices, lessons learnt and “do-different” innovations
- Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 7+ years of experience in IP/SoC PD flows
- Should have led and owned the tapeouts of couple of large, hierarchical SOC designs with high frequency requirements, preferably ARM based architecture
- Expertise in advanced low power techniques and tools such as UPF/CPF and power aware implementation
- Deep understanding of system level performance analysis to be able to partition and timing close the design effectively to meet PPA
- Well versed with CDN based EDA tools such as Genus, Innvous, Tempus and Reliability Signoff tools and should have implemented the same on hierarchical designs
- Strong in digital design fundamentals, computer organization & architectures and bus protocols
- Good understanding of SoC Debug architectures, Design-for-Debug, Design-for-Test
- Strong written and verbal communication skill with the ability to explain and present complex ideas
- Passionate about mentoring and developing people in their careers
- 7+ years of Physical Design experience
If you are interested in this position, please apply to this requisition. Engineering
