Lead Physical Design Engineer
About the job
Job Description
- IP/Block PnR
- Floor-planning, Placement
- EDA tools expertise
- TSMC 5nm experience
- Scripting skills
- Timing closure (STA)
- Signoff checks (FEV)
- VCLP, EMIR, PV
About the job
JD for PD – 8+ years’ experience
• IP/Block level PnR activities from Netlist to GDS-II.
• Good knowledge of all PnR activities like Floor-planning, Placement, CTS, Routing, Timing closure(STA), signoff checks like FEV, VCLP, EMIR and PV.
• Knowledge of industry standard EDA tools (Synopsys, Cadence, Mentor)
• Worked on DSM technologies, tsmc 5nm and below experience preferred.
• Knowledge of scripting skills.
• Minimum Experience: 8+ years
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