In this position you will be delivering compelling timing sign-off methodology to Intel foundry customers and enable best in class PPA on Intel technology. Working closely with EDA vendors, improve and validate flows for industry standard tools used for timing sign-off flow. Develop custom flows for validating EDA tool features. Collaborate with technology leads, VLSI physical design, and timing engineers to understand impact of variation, aging, power delivery network, etc. and deploy nuanced strategies of timing signing off. Work on various aspects of STA, constraints, timing and power optimization.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Preferred Qualifications:
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$169,820.00-$239,750.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 05/02/2025