Senior Power-Management Architect

6 Months ago • 3-10 Years

Job Summary

Job Description

Join a cutting-edge hardware startup in Silicon Valley as a Senior Power-Management Architect. This role focuses on defining, modeling, and optimizing Power/Performance features for RISC-V based Accelerated computing platforms. You will collaborate with talented engineers to create designs that enhance performance, energy efficiency, and scalability in a creative and flexible work environment. Responsibilities include analyzing power behavior of workloads, defining power management features and heuristics, integrating them into firmware and simulation models, and driving platform and system-level PnP targeted framework development. You will also work with design teams to ensure product-level quality and assist with post-silicon bringup and characterization.

Must have:

CPU/GPU/SoC power-management control firmware architecture and coding
GPU/ML workload PnP analysis at system, server and rack level
Power-management feature definition (power capping, thermal control, current capping, DVFS)
Ability to work collaboratively in a fast-paced environment
Go-getter capable of initiating and driving tasks

Good to have:

Power and/or performance modeling using simulators

Perks:

Fun, creative, and flexible work environment

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Job Details

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Senior Power-Management Architect, focused on defining, modeling and optimizing Power/Performance features on a cutting-edge design. Our mission is to reimagine silicon and create RISC-V based Accelerated computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

As a Power Management Architect, you will own or participate in the following:
Work closely with the Performance team to analyze power behavior of workloads of interest on Rivos’ architecture
Work closely with the Performance team to analyze rack-level power and performance
Define and extend the power management features and heuristics, to maximize performance on workloads of interest under power and current constraints
Work closely with the FW and SW teams to integrate the heuristics into the FW code and simulation model. As well as rack-level power-optimization infrastructures
Work closely with the performance teams to help drive platform and system level PnP targeted framework development
Work closely with micro architecture and design teams to bring the new features to product level quality
Collaborate with the performance simulation teams to prototype the features and analyze their benefits pre-silicon
Assist with post-silicon bringup and characterization of the power-management architecture on RIvos’ devices.

Requirements

BS/MS degree in CS/CE/EE or equivalent experience
Experience with CPU/GPU/SoC power-management control firmware architecture and coding
Experience with GPU/ML workload PnP analysis at the system, server and rack level
Experience with the related power-management architecture feature definition such as power capping, thermal control, current capping, and DVFS
Good understanding of power and/or performance modeling using simulators is preferred
Ability to work collaboratively in a fast-paced and dynamic environment
Go-getter capable of initiating and driving tasks from start to finish with minimum technical oversight

Education and Experience

BS (5-10 years of experience) or MS (3-5 years of experience) with a degree in CS/CE/EE or equivalent field, The team already includes senior engineers who will collaborate on feature definition and mentoring.