Senior DFT Methodology - Data Analytics Engineer

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.

Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What you'll be doing:

• As a senior member in our team, you will work with pre-silicon and post-silicon data analytics - visualization, insights and modeling.

• You will work with multi-functional teams, implementing brand-new methodologies for improving our outgoing quality of chips including advanced fault modeling and Silicon Lifecycle Management.

• You will work on hard-to-solve problems in the Design For Test space which will involve application of algorithm design, using statistical tools to analyze and interpret complex datasets and explorations using Applied AI methods.

• In addition, you will help develop and deploy DFT methodologies for our next generation products while also exploring LLM-based solutions.

• You will also help mentor junior engineers on test designs and trade-offs including cost and quality.

What we need to see:

• BSEE (or equivalent experience) with 7+, MSEE with 5+, or PhD with 3+ years of experience in low-power DFT, Data Visualization, Applied Machine Learning or Database Management.

• Understanding of fundamental DFT topics, such as, fault modeling, ATPG and fault simulation.

• Experience in advanced fault models and Silicon Data Corruption is a plus.

• Experience in application of AI for EDA-related problem-solving is a plus.

• Excellent knowledge in using statistical tools for data analysis & insights.

• Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power.

• Experience in Silicon debug and bring-up on the ATE or SLT platforms.

• Strong programming and scripting skills in Perl, Python, C++ or Tcl desired.

• Outstanding written and oral communication skills with the curiosity to work on rare challenges.