Silicon RTL Design Engineer, TPU
Job Summary
Job Description
- Bachelor's degree in related field
- 3+ years ASIC/SoC development (Verilog/SystemVerilog)
- Micro-architecture and IP/Subsystem design experience
- ASIC design verification, synthesis, timing/power analysis, DFT
- Python, C/C++, Perl programming
- SoC design and integration flows
- Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC, memory hierarchies
- High-performance and low-power design techniques
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
- Experience in micro-architecture and design of IPs and subsystems.
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Preferred qualifications:
- Experience with programming languages (e.g., Python, C/C++ or Perl).
- Experience in SoC designs and integration flows.
- Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.
- Knowledge of high performance and low power design techniques.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
You will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with performance, power, and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design and more to specify and deliver high quality designs for next generation data center accelerators.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Own implementation of IPs and subsystems.
- Work with Architecture and Design Leads to understand micro-architecture specifications.
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Identify and drive Power, Performance, and Area improvements for the domains.
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