Community

Home >

Jobs >

ASIC Static Timing Analysis Engineer, Silicon

ASIC Static Timing Analysis Engineer, Silicon

1 Month ago • 12 Years + • Research & Development

About the job

2 skills required for this role

Add these skills to join the top 1% applicants for this job

unity

innovation

Job Description

As an ASIC Static Timing Analysis Engineer at Google, you'll be responsible for driving sign-off timing convergence for high-performance designs. This involves setting up timing constraints, defining the overall STA methodology, and establishing the STA infrastructure and sign-off convergence flows. You'll collaborate with block owners to achieve sign-off timing convergence. The role requires extensive experience in silicon timing closure and chip integration, proficiency in STA tools (PrimeTime, Tempus, etc.), and expertise in constraint authoring for full-chip tape-out. You will contribute to the development of custom silicon solutions powering Google's direct-to-consumer products, impacting millions of users globally. The work involves pushing boundaries and shaping the next generation of hardware experiences.

Must have:

12+ years in silicon timing closure & chip integration
STA sign-off constraint authoring experience
Proficiency in STA tools (PrimeTime, Tempus, etc.)
Full-chip level tape-out sign-off experience
Experience with timing ECO using Tweaker, Primeclosure, DMSA

Good to have:

Master's degree in EE or related field
Experience extracting design parameters & analyzing data trends
Knowledge of semiconductor device physics

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
12 years of experience in silicon timing closure and chip integration.
Experience with STA sign-off constraint authoring for full-chip level, tape-out sign-off requirements, checklists, and associated automation.
Experience in one or more static timing tools: PrimeTime, Tempus, Timing Closure, STA, Timing ECO using Tweaker, Primeclosure, DMSA.

Preferred qualifications:

Master's degree in Electrical Engineering, or in a related technical field.
Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
Knowledge of semiconductor device physics and transistor characteristics.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Drive the sign-off timing convergence for high performance designs.
Set up timing constraints, defining the overall Static Timing Analysis (STA) methodology.
Set up the STA infrastructure and sign-off convergence flows.
Work with block owners throughout the project for sign-off timing convergence.

View Full Job Description

Upload your resume, increase your shortlisting chances by 80%

About The Company

Google

2005 Active Jobs

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.