Jobs

Scholarships

Courses

Companies

Placements

Community

Home >

Jobs >

Silicon Digital Design Engineer III

California, United States (On-site)

Silicon Digital Design Engineer III

1 Hour ago • 3 Years + • Research & Development

About the job

2 skills required for this role

Add these skills to join the top 1% applicants for this job

innovation

cross-functional

Job Description

This Silicon Digital Design Engineer III role at Google involves designing custom silicon solutions for direct-to-consumer products. Responsibilities include RTL coding, simulation debugging, Lint/CDC/FV/UPF checks, test plan participation, and collaborating with cross-functional teams to debug failures. The ideal candidate possesses a Bachelor's degree (Master's or PhD preferred) in a related field and 3+ years of experience in digital logic design, RTL design using Verilog or SystemVerilog, logic synthesis, and low-power design techniques. Experience with ASIC design methodologies and knowledge in areas like processor cores, buses, or verification are highly beneficial. The role contributes to the innovation behind Google's hardware, delivering high performance and efficiency.

Must have:

3+ years digital logic design experience
RTL design (Verilog/SystemVerilog)
Logic synthesis & low-power design
RTL coding, simulation, debugging
Collaboration with cross-functional teams

Good to have:

Master's/PhD in EE/CE/CS
ASIC design methodologies
Processor core, bus/fabric knowledge
ASIC verification or DFT knowledge
High-performance/energy-efficient design

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
Experience in ASIC design flows and methodologies.
Domain knowledge in one of these areas: Processor Cores, Buses/Fabric/NoC, Debug/Trace, Interrupts or Clocks/Reset.
Knowledge of high performance and energy efficient design techniques.
Knowledge of ASIC Verification or DFT.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in test plan and coverage analysis of the sub-system and SOC-level verification.
Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).

View Full Job Description

$127.0K - $187.0K/yr (Outscal est.)

$157.0K/yr avg.

Mountain View, California, United States

Upload your resume, increase your shortlisting chances by 80%

About The Company

Google

2744 Active Jobs

A problem isn't truly solved until it's solved for all. Googlers build products that help create opportunities for everyone, whether down the street or across the globe. Bring your insight, imagination and a healthy disregard for the impossible. Bring everything that makes you unique. Together, we can build for everyone.