Design Verification Engineer, Security

This Design Verification Engineer role at Google focuses on verifying complex security hardware IPs at both IP and subsystem levels. Responsibilities include planning verification, creating and enhancing verification environments using System Verilog and UVM, identifying and writing coverage measures, debugging tests with design engineers, closing coverage gaps, and collaborating with cross-functional teams (Software, Silicon Validation, Silicon bring-up). The ideal candidate possesses 3+ years of experience in verifying IP or digital systems including CPUs, DMA, interconnects, MMUs, peripherals, and memories. Proficiency in verification methodologies (UVM), System Verilog Assertions (SVA), and assertion-based verification is crucial. Experience with security block verification, hardware security modules, crypto blocks, and fault injection is preferred. Perl or Python scripting skills for DV flow development or enhancement are also beneficial.