Senior Mask Designer

3 Months ago • 5 Years + • Research & Development

Job Summary

Job Description

NVIDIA seeks a Senior Digital/Memory Mask Design Engineer to contribute to the design of high-speed digital memory circuits. Responsibilities include implementing IC layout in advanced CMOS process nodes (3nm, 5nm, 7nm, and lower), delivering layouts for full-custom memory groups specializing in digital memory circuits, adopting best layout practices, and following company procedures. The role requires expertise in Cadence EDA tools, high-performance memory layout, and layout verification (EM/IR checks, LOD, Dummification, etc.). This position involves working with various types of bitcells, decoders, and I/O components, and requires knowledge of floor planning, routing, and macro-level assembly.
Must have:
  • 5+ years experience in Memory layout
  • Expertise in Cadence EDA tools
  • Knowledge of high-performance memory layout
  • Layout verification (EM/IR, LOD, Dummification)
  • Understanding of bitcells, decoders, LIO

Job Details

We are looking for a Senior Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.

What you'll be doing:

  • Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.

  • Deliver layouts for Full Custom Memory group specializing in digital Memory circuits.

  • IP layout will comprise of significant digital components.

  • Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts

  • Follow company procedures and practices for IC layout activities.

What we need to see:

  • B.E/B Tech. / M Tech in Electronics or equivalent experience with 5+ Years of proven experience in Memory layout in advanced CMOS process.

  • Detailed knowledge of industry standard EDA tools for Cadence.

  • Experience with layout of high-performance memories of various types.

  • Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)

  • Experience with floor planning, block level routing and macro level assembly.

  • Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.

We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status

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About The Company

Since its founding in 1993, NVIDIA (NASDAQ: NVDA) has been a pioneer in accelerated computing. The company’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined computer graphics, ignited the era of modern AI and is fueling the creation of the metaverse. NVIDIA is now a full-stack computing company with data-center-scale offerings that are reshaping industry.

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