Formal Verification Engineer, Silicon

20 Hours ago • 3 Years + • Research & Development

Job Summary

Job Description

This role involves performing formal verification of complex ASIC designs at Google Cloud. Responsibilities include planning formal verification strategies, creating properties and constraints for design blocks, utilizing formal verification tools, resolving complex verification issues, and improving verification methodologies. Close collaboration with design and verification engineers is crucial to defining design intent and constraints. The work contributes to enhancing formal verification results and implementing reusable components. The position requires expertise in verification methodologies (UVM, SystemVerilog), temporal assertion languages (SVA, PSL), and preferably experience with formal verification tools (JasperGold, VC Formal, etc.).
Must have:
  • Bachelor's degree in EE/CS or equivalent
  • 3+ years verification experience (UVM, SystemVerilog)
  • Experience with testbenches, test cases, and environments
  • Experience with main interconnects, DMA, controllers, power management
  • Temporal assertion language (SVA, PSL) experience
Good to have:
  • Master's/PhD in EE/CS
  • Formal verification tool experience (JasperGold, VC Formal, etc.)
  • Understanding of formal verification algorithms
  • Proficiency in Python scripting

Job Details

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • 3 years of experience with verification methodologies and languages (e.g., UVM, SystemVerilog).
  • Experience developing and maintaining verification testbenches, test cases, and test environments.
  • Experience working on main interconnects, DMA, controllers, and power management, and capturing design specifications in a temporal assertion language (e.g., SVA, PSL).

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering or Computer Science.
  • Knowledge of and experience working with one or more formal verification tools (E.G., JasperGold, VC Formal, Questa Formal, or 360-DV).
  • Understanding of formal verification algorithms.
  • Proficiency with scripting languages (e.g. Python).

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

In this role, you'll perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You'll also help define and improve design and verification methodologies that allow you to achieve formal verification closure.

The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
  • Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
  • Resolve difficult to verify properties. Contribute improvements to methodologies to enhance formal verification results.
  • Architect and implement reusable formal verification components.

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