ASIC Engineer, RTL Integration

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation.
• 3 years of experience with the Register-Transfer Level quality check tool flows (e.g., Lint, Clock Domain Crossing, Reset Domain Crossing, Synthesis).

Preferred qualifications:

• Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).
• Experience with IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols and ASIC methodology.
• Experience with methodologies for low power estimation, timing closure, synthesis.
• Knowledge in one or more of these areas: Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin Multiplexing