Physical Design Lead, Static Timing Analysis
Job Summary
Job Description
- 10+ years STA experience
- Full chip timing signoff
- EDA tool expertise (Primetime, etc.)
- Constraint authoring & verification
- Timing ECO creation
- Methodology development
- 15+ years STA experience
- Leadership in physical design
- Data analysis & QoR metrics
- Semiconductor device physics knowledge
- SPICE simulation experience
- Bonus
- Equity
- Benefits
3 skills required
Job Details
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
- 10 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
- Experience with Electronic design automation (EDA) tools (i.e. Primetime, Tempus, Timevision, STAR-RC) and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk).
Preferred qualifications:
- 15 years of experience in the domain of static timing analysis.
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Knowledge of semiconductor device physics and Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and full-chip static timing topics, including clocking, timing exceptions, time budgeting, IO interface timing, ECOs, and constraint verification.
About the job
In this role, you will work on the physical implementation of Application-specific integrated circuits (ASIC) using advanced technology nodes. You will work on timing margin derivation, constraint development and validation, and timing closure of large, complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. You will perform technical evaluations of vendors, tools, methodologies, and will provide recommendations. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to understand and implement their requirements.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Own chip timing constraint creation and validation, timing sign-off margins and checklist criteria. Perform full chip timing analysis and timing Engineering Change Order (ECO) creation, and oversee final timing sign-off for complex Application-specific integrated circuits (ASIC).
- Lead both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
- Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
- Perform technical evaluations of Electronic design automation (EDA) tools and provide recommendations, documentation, and training.
- Debug flow issues reported by your wider team and work with EDA vendors to resolve them where necessary.
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