Job Description
As a Principal Design Engineer, you will be responsible for scheduling, designing, developing, and supporting IP models of system-level memory. This includes SDRAM, NAND Flash, eMMC, and others, for use on hardware-based verification products. You will also be involved in updating, maintaining, and documenting existing products, designing RTL, and collaborating with customers. Excellent communication and independent R&D skills are required. Regular interaction with customers and mentoring less experienced engineers is expected. Team processes and process improvement will also be a part of your responsibilities.
Good To Have:
- Verification experience using Cadence simulation and/or emulation products.
- Programming experience with scripting languages like Perl, TCL, C-shell.
- Verification experience using UVM test environments.
- Experience in memory sub-system design and operation.
Must Have:
- BSEE with 7+ years industry experience or MSEE with 5+ years.
- Excellent written and spoken English communication skills.
- Expert level knowledge of RTL design using Verilog/SystemVerilog.
- Experience using RTL verification tools and flows.
- Debugging experience.
- Experience with team-wide collaboration tools and process.
- Ability to schedule workload and plan own tasks effectively.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
As a Principal Design Engineer you will be responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products. Additional responsibilities include the following:
- Updating, maintaining, documenting, and supporting existing system level memory model products.
- Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP.
- Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification.
- Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality.
- Must be able to analyze customer & vendor protocol requirements and execute on complex projects from requirement to delivery to post-delivery support
- Communication & collaboration with peers & internal partners as well as strong individual/independent R&D skills are required.
- Regular field AE & external customer interaction and representing Cadence to external customers is required for support of memory models. Must be able to facilitate discussions with AE & customer.
- Ability to mentor less experienced engineers &/or participate in cross-functional projects
- Must participate in team processes as well as evaluate and recommend process improvements.
Required Experience:
- The position requires BSEE with at least 7 yrs of industry experience in designing hardware systems OR a MSEE with at least 5 years of experience in designing hardware systems
- Must have excellent communication skills with both written and spoken English.
- Expert level knowledge of RTL design using languages Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
- Debugging experience.
- Experience with team-wide collaboration tools and process.
- Drive and ability to schedule workload and plan own tasks effectively.
Strongly recommended:
- Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended.
- Verification experience using UVM test environments is highly desired.
- Experience in memory sub-system design and operation is strongly recommended.
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