Design Verification Intern

1 Month ago • All levels

Job Summary

Job Description

The Design Verification Intern will be responsible for understanding design specifications and developing test and coverage plans. This role involves creating constrained random verification environments and components, and writing tests, sequences, functional coverage, and assertions to meet verification goals. The ideal candidate will possess a strong understanding of SV/UVM, Verilog/VHDL/C/C++, and scripting languages like Perl/Python/Shell. They should also have good debugging skills and the ability to work in a fast-paced, dynamic environment. The candidate must be open to continuous personal development and growth to meet the evolving demands of the semiconductor industry.
Must have:
  • Understanding of SV/UVM.
  • Good knowledge of Verilog/VHDL/C/C++.
  • Experience in any scripting language like Perl/Python/Shell.
  • Good debugging skills.
Good to have:
  • Familiarity with ARM/CPU architectures.
  • Knowledge of protocols like UART, I2C, SPI, JTAG.
  • Knowledge of AMBA protocols (AXI/AHB/APB).
  • Hands-on experience in writing tests/sequences/functional coverage.
  • Prior experience with Cadence verification tools and flows is highly desirable.

Job Details

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Seeking Design Verification engineer who can understand Design specification and develop test/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals.

 

Job Description

Understand Design specification and develop test/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals.

 

Required experience.

  • Understanding of SV/UVM.
  • Good knowledge of Verilog/Vhdl/C/C++
  • Experience in any scripting language Perl/Python/Shell.
  • Good debugging skills.

 

Desirable skills and experience

  • Familiarity with ARM/CPU architectures.
  • Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
  • Knowledge of AMBA protocols. (AXI/AHB/APB).
  • Hands on experience in writing tests/sequences/functional coverage.
  • Prior experience with Cadence verification tools and flows is highly desirable.

 

Strong vocabulary, communication, planning, and presentation skills are essential. Ability to work with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing to take up additional responsibilities to contribute to team’s success.

We’re doing work that matters. Help us solve what others can’t.

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About The Company

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

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