As a Staff Engineer - IP Design, you will deliver standards-compliant IP blocks for CXL/PCIE in FPGAs or ASICs. You will lead ASIC or FPGA projects and streamline the ASIC development process with advanced tools and scripting. You will manage projects, architect, develop and document designs using Verilog, and create verification environments with System Verilog and UVM. This role also involves developing test cases, tracking bug reports, planning staffing, and providing oversight to employees. Additionally, you will foster teamwork and support employee development. You will report to the Director of the Design Team.